Transient voltage suppression device and manufacturing method therefor

Patent metadata

Field	Value
Publication number	US-12015025-B2
Application number	US-201917265549-A
Country	US
Kind code	B2
Filing date	Aug 15, 2019
Priority date	Aug 31, 2018
Publication date	Jun 18, 2024
Grant date	Jun 18, 2024

Abstract

A transient voltage suppression device includes: a substrate; a first conductive type well region including a first well and a second well; a second conductive type well region including a third well and a fourth well, the third well being disposed between the first well and the second well so as to isolate the first well and the second well, and the second well being disposed between the third well and the fourth well; a zener diode active region; a first doped region, provided in the first well; a second doped region, provided in the first well; a third doped region, provided in the second well; a fourth doped region, provided in the second well; a fifth doped region, provided in the zener diode active region; and a sixth doped region, provided in the zener diode active region.

First claim

What is claimed is:

1. A transient-voltage suppression device, comprising:
a substrate of a second conductivity type;
a first-conductivity-type well region disposed in the substrate and including a first well and a second well;
a second-conductivity-type well region disposed in the substrate and including a third well and a fourth well, the third well being disposed between the first well and the second well to isolate the first well and the second well from each other, and the second well being disposed between the third well and the fourth well; the first conductivity type and the second conductivity type being conductivity types opposite to each other;
a zener diode active region disposed in the fourth well and being of the second conductivity type;
a first doped region being of the first conductivity type and disposed in the first well;
a second doped region being of the second conductivity type and disposed in the first well;
a third doped region being of the first conductivity type and disposed in the second well;
a fourth doped region being of the second conductivity type and disposed in the second well;
a fifth doped region being of the first conductivity type and disposed in the zener diode active region; and
a sixth doped region being of the second conductivity type and disposed in the zener diode active region;
wherein the fourth doped region is used as an anode region of a first diode, the first doped region is used as a cathode region of a second diode, and an electrical connection between the first doped region and the fourth doped region is used as a first potential terminal; the third doped region is used as a cathode region of the first diode, the fifth doped region is used as a cathode region of a zener diode, and an electrical connection between the third doped region and the fifth doped region is used as a second potential terminal; and the second doped region is used as an anode region of the second diode, the sixth doped region is used as an anode region of the zener diode, and an electrical connection between the second doped region and the sixth doped region is used as a third potential terminal;
isolation of the first well from the second well by the third well is equivalent to isolation of the first diode from the second diode;
the Zener diode active region has a doping concentration different than that of the fourth well;
wherein the Zener diode active region has phosphorus doping ions and boron doping ions, and a doping concentration of the phosphorus doping ions is less than that of the boron doping ions;
wherein the first well and the second well are deep N-wells; the third well, the fourth well, and the fifth well are deep P-wells; and the first-conductivity-type well region and the second-conductivity-type well region are formed by drive-in a long time of 250 to 350 minutes at high temperatures of 1000 to 1300 degree Celsius.

2. The transient-voltage suppression device of claim 1 , wherein the first potential terminal is adapted to be electrically connected to an input/output terminal, the second potential terminal is adapted to be electrically connected to a working-voltage terminal, and the third potential terminal is adapted to be connected to ground.

3. The transient-voltage suppression device of claim 1 , wherein the first-conductivity-type well region and a second-conductivity-type well region have a junction depth in a range of 7 micrometers to 15 micrometers.

4. The transient-voltage suppression device of claim 1 , wherein the first conductivity type is N-type, and the second conductivity type is P-type.

5. The transient-voltage suppression device of claim 1 , wherein the second-conductivity-type well region further comprises a fifth well, and the first well is disposed between the third well and the fifth well.

6. The transient-voltage suppression device of claim 1 , wherein two second doped regions are disposed in the first well, two third doped regions are disposed in the second well, and two sixth doped regions are disposed in the fourth well.

7. The transient-voltage suppression device of claim 1 , wherein the transient-voltage suppression device further comprises:
a first isolation structure disposed between the first doped region and the second doped region and isolating the first doped region and the second doped region from each other;
a second isolation structure disposed between the third doped region and the fourth doped region and isolating the third doped region and the fourth doped region;
a third isolation structure disposed between two closest doped regions in the first well region and the second well region and isolating the two doped regions from each other; and
a fourth isolation structure disposed between two closest doped regions in the second well region and the fourth well region and isolating the two doped regions from each other.

8. The transient-voltage suppression device of claim 7 , wherein the first through fourth isolation structures are made of an oxide insulating material.

9. A method for manufacturing a transient-voltage suppression device, the transient-voltage suppression device including a first diode, a second diode, and a zener diode, an electrical connection between an anode of the first diode and a cathode of the second diode being used as a first potential terminal, an electrical connection between a cathode of the first diode and a cathode of the zener diode being used as a second potential terminal, and an electrical connection between an anode of the second diode and an anode of the zener diode being used as a third potential terminal, wherein the method comprises:
forming a mask layer on a substrate of a second conductivity type, and then performing lithography and etching the mask layer to expose a doping window of a first-conductivity-type well region;
doping the substrate with first-conductivity-type ions through the doping window of the first-conductivity-type well region to form a first region on a surface of the substrate;
growing an oxide layer as a doping blocking-layer in the first region;
removing the mask layer, and doping areas of the surface of the substrate not covered by the doping blocking-layer with second-conductivity-type ions to form a second region, a first conductivity type and the second conductivity type being conductivity types opposite to each other;
performing a thermal drive-in to enable the first region to diffuse to form a first well and a second well, and enable the second region to diffuse to form a third well and a fourth well, the third well being located between the first well and the second well to isolate the first well and the second well from each other, the second well being located between the third well and the fourth well; and
forming, after the doping blocking-layer is removed, respectively a first doped region, a second doped region, a third doped region, a fourth doped region, a fifth doped region, a sixth doped region, and a zener diode active region by lithographing and doping;
wherein the zener diode active region is located in the fourth well and is of the second conductivity type; the first doped region is of the first conductivity type and is located in the first well; the second doped region is of the second conductivity type and is disposed in the first well;
the third doped region is of the first conductivity type and is disposed in the second well; the fourth doped region is of the second conductivity type and is disposed in the second well; the fifth doped region is of the first conductivity type and is disposed in the zener diode active region; and the sixth doped region is of the second conductivity type and is disposed in the zener diode active region; and
wherein the Zen

Assignees

• Csmc Technologies Fab2 Co Ltd

Inventors

• Cheng Shikang
• Gu Yan
• Zhang Sen

Classifications

• H10P58/00

  Singulating wafers or substrates into multiple chips, i.e. dicing · CPC title

• H10D62/126

  Top-view geometrical layouts of the regions or the junctions · CPC title

• H10D8/25

  Zener diodes · CPC title

• H10D8/022

  of Zener diodes · CPC title

• H10D89/611 Primary

  using diodes as protective elements · CPC title