ESD protection device

Patent metadata

Field	Value
Publication number	US-9633989-B2
Application number	US-201514835959-A
Country	US
Kind code	B2
Filing date	Aug 26, 2015
Priority date	Feb 28, 2013
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

An ESD protection device includes a zener diode, and a series circuit of diodes and a series circuit of diodes that are connected in parallel with the zener diode. At the connection point between the diodes, an Al electrode film is formed on the surface of a Si substrate, and at the connection point between diodes, an Al electrode film is formed on the surface of the Si substrate. The diodes are formed on the surface of the Si substrate, and the diodes are formed in the thickness direction of the Si substrate. The Si substrate has a longitudinal direction and a shorter direction orthogonal to the longitudinal direction in planar view, and the Al electrode films are formed respectively at both ends in the shorter direction of the Si substrate. Thus, provided is an ESD protection device which suppresses the ESL, and keeps the clamp voltage low.

First claim

The invention claimed is:

1. An electro static discharge (ESD) protection device comprising:
a zener diode formed in a semiconductor substrate;
a first series circuit formed in the semiconductor substrate and coupled in parallel to the zener diode, the first series circuit having first and second diodes;
a second series circuit formed in the semiconductor substrate and coupled in parallel to the zener diode, the second series circuit having third and fourth diodes connected in series;
a first input/output electrode disposed on the surface of the semiconductor substrate and coupled to a first node between the first and second diodes; and
a second input/output electrode disposed on the surface of the semiconductor substrate and coupled to a second node between the third and fourth diodes,
wherein the first diode comprises two diodes electrically coupled in parallel between the first node and the zener diode, with the two diodes extending in a planar direction of the semiconductor substrate.

2. The ESD protection device according to claim 1 , wherein the first series circuit and the second series circuit are and aligned in a same direction as the zener diode.

3. The ESD protection device according to claim 1 , wherein the first diode and the third diode are formed on the surface of the semiconductor substrate.

4. The ESD protection device according to claim 3 , wherein the second diode and the fourth diode are formed in a thickness direction of the semiconductor substrate.

5. The ESD protection device according to claim 4 ,
wherein the semiconductor substrate has a first length in a longitudinal direction and a second length shorter than the first length that is in a direction orthogonal to the longitudinal direction in a planar view of the semiconductor substrate, and
wherein the first input/output electrode and the second input/output electrode are formed at both ends in the shorter direction of the semiconductor substrate.

6. The ESD protection device according to claim 1 , further comprising a rewiring layer disposed on the surface of the semiconductor substrate.

7. The ESD protection device according to claim 6 , wherein the rewiring layer comprises:
a first wiring electrode and a second wiring electrode opposed to the surface of the semiconductor substrate;
a first contact hole that electrically connects the first input/output electrode and at least a portion of the first wiring electrode; and
a second contact hole that electrically connects the second input/output electrode and at least a portion of the second wiring electrode.

8. The ESD protection device according to claim 7 , wherein the rewiring layer further comprises a first opening and a second opening formed in planar view, the first opening and the second opening partially exposing the first wiring electrode and the second wiring electrode.

9. The ESD protection device according to claim 8 , wherein the first opening and the second opening are formed at both ends in the longitudinal direction of the semiconductor substrate.

10. The ESD protection device according to claim 1 , wherein either of the two diodes of the first diode is connected in series to the second diode and with the second diode connected collectively in parallel to the zener diode.

11. The ESD protection device according to claim 1 , wherein the third diode comprises two diodes opposite to each other in the forward direction from the second input/output electrode in the planar direction of the semiconductor substrate.

12. The ESD protection device according to claim 11 , wherein either of the two diodes of the third diode is connected in series to the fourth diode and with the fourth diode connected collectively in parallel to the zener diode.

13. The ESD protection device according to claim 1 , wherein the semiconductor substrate is a p+ type substrate.

14. The ESD protection device according to claim 13 , wherein a p well and an n+ diffusion layer are formed in the p+ type substrate to form the zener diode in the thickness direction of semiconductor substrate.

15. The ESD protection device according to claim 14 , wherein an n-epitaxial layer and n+ diffusion layers are formed in the p+ type substrate to form each of the second and fourth diodes.

16. The ESD protection device according to claim 15 , wherein n wells are formed in the n-epitaxial layer and p+ diffusion layers and additional n+ diffusion layers form the first diode and the third diode on the surface of the semiconductor substrate.

17. An electro static discharge (ESD) protection device comprising:
a zener diode formed in a semiconductor substrate;
a first circuit formed in the semiconductor substrate, the first series circuit having a first diode and a second diode aligned in a forward direction and connected in series, and aligned in the forward direction and connected in parallel with the zener diode;
a second circuit formed in the semiconductor substrate, the second series circuit having a third diode and a fourth diode aligned in a forward direction and connected in series, and aligned in the forward direction and connected in parallel with the zener diode;
a first input/output electrode connected to a connection point between the first diode and the second diode, and formed on the surface of the semiconductor substrate; and
a second input/output electrode connected to a connection point between the third diode and the fourth diode, and formed on the surface of the semiconductor substrate,
wherein the first diode and the third diode are disposed on the surface of the semiconductor substrate,
the second diode and the fourth diode are disposed in a thickness direction of the semiconductor substrate,
the first diode comprises two diodes electrically coupled in parallel between the first input/output electrode and the second input/output electrode, with the two diodes extending in the planar direction of the semiconductor substrate,
the third diode comprise two diodes electrically coupled in parallel between the second input/output electrode and the first input/output electrode, with the two diodes extending in the planar direction of the semiconductor substrate,
the semiconductor substrate has a longitudinal direction and a shorter direction orthogonal to the longitudinal direction in planar view, and
the first input/output electrode and the second input/output electrode are disposed at both ends in the shorter direction of the semiconductor substrate.

18. The ESD protection device according to claim 17 , wherein the two diodes of the first diode are connected in parallel with each other, and the two diodes of the second diode are connected in parallel with each other.

19. The ESD protection device according to claim 17 , further comprising a rewiring layer disposed on the surface of the semiconductor substrate,
wherein the rewiring layer comprises a first wiring electrode and a second wiring electrode opposed to the surface of the semiconductor substrate, a first contact hole that electrically connects the first input/output electrode and a part of the first wiring electrode, and a second contact hole that electrically connects the second input/output electrode and a part of the second wiring electrode,
wherein the rewiring layer has a first opening and a second opening disposed in a planar view, the first opening and the second opening partially exposing the first wiring electrode and the second wiring electrode, and
wherein the first opening and the second opening are disposed at both ends in the longitudinal direc

Assignees

• Murata Manufacturing Co

Inventors

• Kato Noboru
• Nakaiso Toshiyuki

Classifications

• H10W72/07251

  characterised by changes in properties of the bump connectors during connecting · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H01L29/866

  Electricity · mapped topic

• H01L2224/16

  Electricity · mapped topic