Integrated circuits protected by substrates with cavities, and methods of manufacture

Patent metadata

Field	Value
Publication number	US-9899281-B2
Application number	US-201615265148-A
Country	US
Kind code	B2
Filing date	Sep 14, 2016
Priority date	Mar 12, 2014
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

Dies ( 110 ) with integrated circuits are attached to a wiring substrate ( 120 ), possibly an interposer, and are protected by a protective substrate ( 410 ) attached to a wiring substrate. The dies are located in cavities in the protective substrate (the dies may protrude out of the cavities). In some embodiments, each cavity surface puts pressure on the die to strengthen the mechanical attachment of the die the wiring substrate, to provide good thermal conductivity between the dies and the ambient (or a heat sink), to counteract the die warpage, and possibly reduce the vertical size. The protective substrate may or may not have its own circuitry connected to the dies or to the wiring substrate. Other features are also provided.

First claim

The invention claimed is:

1. A method for fabricating an electrically functioning apparatus, the method comprising:
(a) obtaining an assembly comprising:
a first substrate;
one or more modules attached and electrically connected to the first substrate, each module protruding from a top side of the assembly and comprising one or more semiconductor integrated circuits;
(b) forming a first layer on the top side of the assembly, the first layer comprising a top surface of a first material, the top surface overlying one or more first protrusions formed by the one or more modules and comprising a second protrusion over each first protrusion, the top surface comprising a laterally-extending area located at a level below a top of each second protrusion;
(c) obtaining a second substrate comprising one or more cavities; and
(d) after said forming the first layer on the top side of the assembly, bonding the second substrate to the top surface of the first layer, with at least part of each semiconductor integrated circuit being located in a corresponding cavity in the second substrate, a portion of the top surface of the first layer being bonded to a surface of a corresponding cavity in the second substrate, and a portion of the top surface of the first layer being bonded to the second substrate at said laterally-extending area, at least one said laterally-extending area extending outside the corresponding cavity;
wherein said bonding comprises directly bonding the first layer to the second substrate; and
wherein at a conclusion of said bonding, part of the top surface of the first layer is not bonded to the second substrate and is spaced from the second substrate.

2. The method of claim 1 wherein said bonding the second substrate comprises bonding the first layer to the second substrate in an area outside the one or more cavities.

3. The method of claim 2 wherein said bonding the second substrate comprises bonding the first layer to the second substrate around each said cavity.

4. The method of claim 1 wherein the first layer covers each module.

5. The method of claim 1 wherein, for each module, the first layer covers the module and an area adjacent to the module and laterally surrounding the module.

6. The method of claim 1 wherein the first layer covers the assembly.

7. The method of claim 6 wherein an entire top surface of the first layer is continuous.

8. The method of claim 1 wherein the first layer is inorganic.

9. The method of claim 1 wherein the first layer is silicon oxide.

10. The method of claim 1 wherein the first layer is metal.

11. The method of claim 1 wherein the second substrate comprises:
a constituent substrate of a selected material, the one or more cavities extending into the constituent substrate; and
a second layer of a material different from the selected material, the second layer extending into the one or more cavities; and
said bonding comprises directly bonding the first layer to the second layer.

12. The method of claim 1 wherein said part of the top surface of the first layer underlies a surface of at least one said cavity in the second substrate.

13. The method of claim 11 wherein at a conclusion of said bonding, part of the top surface of the first layer is not bonded to the second layer and is spaced from the second layer.

14. The method of claim 13 wherein said part of the top surface of the first layer underlies a surface of at least one said cavity in the second substrate.

15. A method for fabricating an electrically functioning apparatus, the method comprising:
(a) obtaining an assembly comprising:
a first substrate;
one or more modules attached and electrically connected to the first substrate, each module protruding from a top side of the assembly and comprising one or more semiconductor integrated circuits;
(b) forming a continuous first layer on the top side of the assembly, the first layer comprising a top surface of a first material, the top surface overlying one or more first protrusions formed by the one or more modules and comprising a second protrusion over each first protrusion;
(c) obtaining a second substrate comprising one or more cavities; and
(d) after said forming the first layer on the top side of the assembly, bonding the second substrate to the top surface of the first layer, with at least part of each semiconductor integrated circuit being located in a corresponding cavity in the second substrate, and a top of each second protrusion of the top surface of the first layer being bonded to a surface of a corresponding cavity in the second substrate, wherein the first layer extends outside of at least one cavity;
wherein the top surface comprises, for each second protrusion, a first area adjacent to the second protrusion and not bonded to the second substrate, the area being farther from the second substrate than is the second protrusion.

16. The method of claim 15 wherein the top surface further comprises, for each second protrusion, a second area separated from the second protrusion by the first area; and
the second substrate is directly bonded to the top surface of the first layer at the top of each second protrusion and at each second area.

17. A method for fabricating an electrically functioning apparatus, the method comprising:
(a) obtaining an assembly comprising:
a first substrate;
one or more modules attached and electrically connected to the first substrate, each module protruding from a top side of the assembly and comprising one or more semiconductor integrated circuits;
(b) forming a continuous first layer on the top side of the assembly, the first layer comprising a top surface of a first material, the top surface overlying one or more first protrusions formed by the one or more modules and comprising a second protrusion over each first protrusion;
(c) obtaining a second substrate comprising one or more cavities, the second substrate comprising:
a constituent substrate of a selected material, the one or more cavities extending into the constituent substrate; and
a second layer of a material different from the selected material, the second layer comprising a bottom surface extending into the one or more cavities; and
(d) after said forming the first layer on the top side of the assembly, bonding the bottom surface of the second layer to the top surface of the first layer, with at least part of each semiconductor integrated circuit being located in a corresponding cavity in the second substrate, and at least a portion of each second protrusion of the top surface of the first layer being bonded to the bottom surface of the second layer in a corresponding cavity in the second substrate, and with at least part of the top surface of the first layer in the corresponding cavity not being bonded to the second layer and being farther from the second layer than a top of the second protrusion.

Assignees

• Invensas Corp

Inventors

• Shen Hong
• Woychik Charles G
• Sitaram Arkalgud R

Classifications

• H10P14/47

  Electrolytic deposition, i.e. electroplating; Electroless plating · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title