Semiconductor memory device having composite dielectric film structure and methods of forming the same

Patent metadata

Field	Value
Publication number	US-12014966-B2
Application number	US-202318115810-A
Country	US
Kind code	B2
Filing date	Mar 1, 2023
Priority date	Feb 23, 2021
Publication date	Jun 18, 2024
Grant date	Jun 18, 2024

Abstract

A semiconductor memory device and method of making the same are disclosed. The semiconductor memory device includes a substrate that includes a memory region and a peripheral region, a transistor including a metal gate located in the peripheral region, a composite dielectric film structure located over the metal gate of the transistor, the composite dielectric film structure including a first dielectric layer and a second dielectric layer over the first dielectric layer, where the second dielectric layer has a greater density than a density of the first dielectric layer, and at least one memory cell located in the memory region. The composite dielectric film structure provides enhanced protection of the metal gate against etching damage and thereby improves device performance.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate including a first region and a second region;
a plurality of memory devices located in the first region;
a plurality of transistors each including a metal gate located in the second region;
a first dielectric layer extending over the plurality of transistors in the second region and over at least a portion of the plurality of memory devices located in the first region; and
a second dielectric layer extending over the first dielectric layer in the first region, wherein the second dielectric layer has a different composition and/or physical characteristics than the first dielectric layer, and the second dielectric layer does not extend over the memory devices in the first region.

2. The semiconductor device of claim 1 , wherein the first dielectric layer contacts an upper surface of each of the metal gates of the plurality of transistors.

3. The semiconductor device of claim 1 , wherein each of the first dielectric layer and the second dielectric layer have a thickness that is between 5 nm and 30 nm.

4. The semiconductor device of claim 1 , wherein the first dielectric layer comprises a dielectric material including at least one of silicon oxide formed using a tetraethoxysilane (TEOS) precursor, and a resist protective oxide (RPO) material.

5. The semiconductor device of claim 1 , wherein the second dielectric layer comprises a dielectric material including at least one of a buffer oxide material, a silicon nitride material, and a high-temperature oxide (HTO) material.

6. The semiconductor device of claim 1 , wherein the first dielectric layer contacts an upper surface of at least one memory device in the first region.

7. The semiconductor device of claim 6 , wherein the at least one memory device comprises:
a floating gate;
a control gate located above the floating gate; and
a select gate located on a first side of the floating gate and the control gate, wherein the first dielectric layer contacts an upper surface of the control gate.

8. The semiconductor device of claim 7 , wherein the at least one memory device further comprises:
an erase gate located on a second side of the floating gate and the control gate, wherein a metal silicide layer is located on an upper surface of the select gate and on an upper surface of the erase gate.

9. The semiconductor device of claim 8 , wherein the first dielectric layer is not located over the metal silicide layer located on the upper surface of the select gate and on the upper surface of the erase gate.

10. A semiconductor device, comprising:
a substrate including a first region and a second region, wherein an upper surface of the substrate is recessed in the first region relative to an upper surface of the substrate in the second region;
a plurality of memory devices located in the first region;
a plurality of transistors each including a metal gate located in the second region; and
a composite dielectric film structure comprising at least two dielectric layers extending over the plurality of transistors in the second region, wherein a lower surface of the composite dielectric film structure is co-planar with an upper surface of each of the memory devices.

11. The semiconductor device of claim 10 , wherein a peripheral edge of the composite dielectric film structure is located within 300 nm of a boundary between the first region and the second region.

12. The semiconductor device of claim 11 , wherein the boundary between a memory region and a peripheral region is defined by a peripheral edge of an isolation feature located in the substrate.

13. The semiconductor device of claim 10 , further comprising a plurality of conductive vias extending through the composite dielectric film structure, wherein the composite dielectric film structure extends continuously between the conductive vias in the second region.

14. The semiconductor device of claim 10 , wherein each of the transistors in the second region includes a metal gate, and the composite dielectric film structure is located over the metal gates of the plurality of transistors in the second region.

15. The semiconductor device of claim 10 , wherein the composite dielectric film structure comprises at least two dielectric layers having different compositions and/or physical characteristics.

16. A method of fabricating a semiconductor device, comprising:
forming a plurality of memory devices in a first region of a substrate;
forming a plurality of transistors, each including a metal gate, in a second region of the substrate;
forming a first dielectric material layer over the plurality of transistors in the second region and over a portion of each of the memory devices in the first region;
forming a second dielectric material layer over the first dielectric layer in the second region, wherein the second dielectric layer does not extend over the plurality of memory devices in the first region;
depositing a metal material layer over the semiconductor device;
heating the metal material layer to form a metal silicide layer over portions of the memory devices that are exposed through the first dielectric layer; and
performing an etching process to remove remaining portions of the metal material layer.

17. The method of claim 16 , wherein forming the first dielectric layer comprises forming the first dielectric layer over each of the metal gates of the plurality of transistors in the second region and over a control gate of each of the plurality of memory devices located in the first region.

18. The method of claim 16 , wherein forming the second dielectric layer comprises forming the second dielectric layer over the first dielectric layer in the second region such that a peripheral edge of the second dielectric layer is located within 300 nm of a boundary between the first region and the second region.

19. The method of claim 16 , wherein the metal material layer is heated to form the metal silicide layer over an upper surface of at least one of a select gate and a control gate of a memory device in the first region, and a portion of the first dielectric layer is located over a control gate of the memory device during the formation of the metal silicide layer and during the etching process to remove the remaining portions of the metal material layer.

20. The method of claim 16 , further comprising:
forming a conductive via through the first dielectric layer and the second dielectric layer and electrically contacting a source or drain region of a transistor in the second region.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Sheng-Chieh
• Wang Wei-Ming
• Lee Ming-Lun
• Hsieh Chih-Ren
• Liu Ming Chyi

Classifications

• H10W74/147

  the encapsulations being multilayered · CPC title

• H10W74/01

  Manufacture or treatment · CPC title

• H10W74/43 Primary

  comprising oxides, nitrides or carbides, e.g. ceramics or glasses · CPC title

• H10D30/6892 Primary

  having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate · CPC title

• H10D64/035

  comprising conductor-insulator-conductor-insulator-semiconductor structures · CPC title