Semiconductor package having an electrically insulating core with exposed glass fibres

Patent metadata

Field	Value
Publication number	US-12014964-B2
Application number	US-202217986306-A
Country	US
Kind code	B2
Filing date	Nov 14, 2022
Priority date	Jan 28, 2020
Publication date	Jun 18, 2024
Grant date	Jun 18, 2024

Abstract

A semiconductor package includes: an electrically insulating core and an electrically conductive first via extending through a periphery region of the core, the core having glass fibres interwoven with epoxy material and one or more regions where the glass fibres are exposed from the epoxy material; a power semiconductor die embedded in an opening in the core and having a first load terminal bond pad which faces a same direction as a first side of the core, a second load terminal bond pad which faces a same direction as a second side of the core, and a control terminal bond pad; a resin that encases the power semiconductor die; a first contact pad plated on the first via at the second side of the core; and a second contact pad plated on the first load terminal bond pad of the power semiconductor die at the first side of the core.

First claim

What is claimed is:

1. A semiconductor package, comprising:
an electrically insulating core having a first side, a second side opposite the first side and configured for mounting to a substrate, and an electrically conductive first via extending through a periphery region of the core, the periphery region defining an opening in the core, the core comprising glass fibres interwoven with epoxy material, the core having one or more regions at the second side where the glass fibres are exposed from the epoxy material;
a power semiconductor die embedded in the opening in the core, the power semiconductor die being thinner than the core and comprising a first load terminal bond pad at a first side which faces a same direction as the first side of the core, a second load terminal bond pad at a second side which faces a same direction as the second side of the core, and a control terminal bond pad at the first side or the second side of the power semiconductor die;
a resin in the opening in the core and that encases the power semiconductor die;
a first contact pad plated on the first via at the second side of the core; and
a second contact pad plated on the first load terminal bond pad of the power semiconductor die at the first side of the core.

2. The semiconductor package of claim 1 , further comprising:
a third contact pad plated on the second load terminal bond pad of the power semiconductor die at the second side of the core.

3. The semiconductor package of claim 2 , further comprising:
a fourth contact pad plated on the control terminal bond pad of the power semiconductor die at the first or second side of the core.

4. The semiconductor package of claim 1 , further comprising:
a solder mask partly covering the one or more regions at the second side of the core where the glass fibres are exposed from the epoxy material.

5. The semiconductor package of claim 1 , wherein the resin is coplanar with the first side of the core and no glass fibres are exposed from the epoxy material at the first side of the core.

6. The semiconductor package of claim 1 , further comprising:
a recess at the second side of the core.

7. The semiconductor package of claim 6 , wherein the recess is deeper than the first contact pad at the second side of the core.

8. The semiconductor package of claim 6 , further comprising:
a solder ball in the recess.

9. The semiconductor package of claim 1 , wherein the second side of the core is dry plasma etched, and wherein the first side of the core is not dry plasma etched.

10. The semiconductor package of claim 1 , wherein the first load terminal bond pad of the power semiconductor die is a drain bond pad, and wherein the second load terminal bond pad of the power semiconductor die is a source bond pad.

11. The semiconductor package of claim 1 , wherein the exposed glass fibres are hidden from plain view when the second side of the core is in a mounted position on a substrate.

Assignees

• Infineon Technologies Ag
• Infineon Technologies Americas Corp

Inventors

• Cho Eung San
• Naeve Tomasz
• Palm Petteri

Classifications

• H10W70/635

  Through-vias · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/926

  Multiple bond pads having different sizes · CPC title

• H10W72/944

  Dispositions of multiple bond pads · CPC title