Performant inline ECC architecture for DRAM controller

Patent metadata

Field	Value
Publication number	US-11093323-B2
Application number	US-201916384614-A
Country	US
Kind code	B2
Filing date	Apr 15, 2019
Priority date	Apr 15, 2019
Publication date	Aug 17, 2021
Grant date	Aug 17, 2021

Abstract

Techniques are disclosed for reducing the time required to read and write data to memory. Data reads and/or writes can be delayed when error correction code (ECC) bits, which are used to detect and/or correct data corruption, are written to memory. Writing ECC bits can take longer in some instances than writing data bits because an ECC write may involve a read/modify/write operation, as opposed to just simply writing the bits to memory. Some latencies associated with writing ECC bits can be hidden by interleaving ECC writes with data writes. However, if insufficient data writes are available for interleaving, hiding such latencies become difficult. Thus, various techniques are disclosed, for example, where ECC writes are deferred until a sufficient number of data writes become available for interleaving. By interleaving ECC writes, the disclosed techniques decrease the overall time required to read and write data to memory.

First claim

What is claimed is:

1. A computer-implemented method, comprising:
determining that an insufficient number of pending write transactions are available for execution during a first period of time to mask one or more latencies associated with executing a first error-correcting code (ECC) write transaction during the first period of time, wherein the first period of time corresponds to when write transactions are scheduled for execution;
in response to determining that an insufficient number of pending write transactions are available, preventing the first ECC write transaction from being scheduled for execution during the first period of time;
determining that a sufficient number of pending write transactions are available to mask the one or more latencies during a second period of time when write transactions are scheduled for execution; and
in response to determining that a sufficient number of pending write transactions are available, scheduling the first ECC write transaction for execution during the second period of time.

2. The computer-implemented method of claim 1 , wherein preventing the first ECC write transaction from being scheduled to execute comprises caching the first ECC write transaction (i) during the first period of time, and (ii) during a subsequent period of time when read transactions are scheduled to execute.

3. The computer-implemented method of claim 1 , further comprising:
determining that a first read transaction targets a memory page associated with the first ECC write transaction; and
servicing the first read transaction using a cached version of the first ECC write transaction.

4. The computer-implemented method of claim 1 , further comprising scheduling one or more write transactions to execute using a first bank associated with a command/data bus during the second period of time, wherein scheduling the first ECC write transaction for execution comprises scheduling the first ECC write transaction to execute using a second bank associated with the command/data bus during the second period of time.

5. The computer-implemented method of claim 4 , wherein:
the first ECC write transaction executes during N clock cycles that occur during the second period of time,
the one or more write transactions include at least N write transaction(s), and
N comprises a positive integer value.

6. The computer-implemented method of claim 1 , wherein the first ECC write transaction is associated with write data that is written to a first memory page during the first period of time.

7. The computer-implemented method of claim 6 , wherein the first ECC write transaction is executed during the second period of time to write ECC data associated with the write data to the first memory page.

8. The computer-implemented method of claim 1 , wherein determining that a sufficient number of pending write transactions are available comprises determining that:
at least a first number of pending write transactions associated with a first group of memory banks are scheduled for execution during the second period of time; and
at least a second number of pending write transactions associated with a second group of memory banks are scheduled for execution during the second period of time.

9. The computer-implemented method of claim 1 , wherein preventing the first ECC write transaction from being scheduled for execution during the first period of time prevents a formation of a bubble on a command/data bus on which the first ECC transaction would have been scheduled for execution during the first period of time.

10. The computer-implemented method of claim 1 , wherein preventing the first ECC write transaction from being scheduled for execution during the first period of time increases utilization of a command/data bus across the first period of time and the second period of time.

11. A system, comprising:
a memory controller that schedules write transactions for execution by performing the steps of:
determining that an insufficient number of pending write transactions are available for execution during a first period of time to mask one or more latencies associated with executing a first error-correcting code (ECC) write transaction during the first period of time, wherein the first period of time corresponds to when write transactions are scheduled for execution;
in response to determining that an insufficient number of pending write transactions are available, preventing the first ECC write transaction from being scheduled for execution during the first period of time;
determining that a sufficient number of pending write transactions are available to mask the one or more latencies during a second period of time when write transactions are scheduled for execution; and
in response to determining that a sufficient number of pending write transactions are available, scheduling the first ECC write transaction for execution during the second period of time.

12. The system of claim 11 , wherein the memory controller prevents the first ECC write transaction from being scheduled to execute by caching the first ECC write transaction (i) during the first period of time, and (ii) during a subsequent period of time when read transactions are scheduled to execute.

13. The system of claim 11 , wherein the memory controller further performs the steps of:
determining that a first read transaction targets a memory page associated with the first ECC write transaction; and
servicing the first read transaction using a cached version of the first ECC write transaction.

14. The system of claim 11 , wherein the memory controller further performs the step of:
scheduling one or more write transactions to execute using a first bank associated with a command/data bus during the second period of time,
wherein scheduling the first ECC write transaction for execution comprises scheduling the first ECC write transaction to execute using a second bank associated with the command/data bus during the second period of time.

15. The system of claim 14 , wherein:
the first ECC write transaction executes during N clock cycles that occur during the second period of time,
the one or more write transactions include at least N write transaction(s), and
N comprises a positive integer value.

16. The system of claim 14 , wherein:
the first ECC write transaction is associated with write data that is written to a first memory page during the first period of time, and
the first ECC write transaction is executed during the second period of time to write ECC data associated with the write data to the first memory page.

17. The system of claim 14 , wherein the memory controller determines that a sufficient number of pending write transactions are available by determining that:
at least a first number of pending write transactions associated with a first group of memory banks are scheduled for execution during the second period of time; and
at least a second number of pending write transactions associated with a second group of memory banks are scheduled for execution during the second period of time.

18. The system of claim 11 , wherein the memory controller prevents the first ECC write transaction from being scheduled for execution during the first period of time to prevent a formation of a bubble on a command/data bus on which the first ECC transaction would have been scheduled for execution during the first period of time.

19. The system of claim 11 , wherein the memory controller prevents the first ECC write transaction from being scheduled for execution du

Assignees

• Nvidia Corp

Inventors

• Pandey Ashutosh
• Gupta Jay
• Agarwal Kaushal
• Bennett Justin
• Madugula Srinivas Santosh Kumar

Classifications

• G06F9/466 Primary

  Transaction processing · CPC title

• G06F2212/1032

  Reliability improvement, data loss prevention, degraded operation etc · CPC title

• G06F11/1044 Primary

  with specific ECC/EDC distribution · CPC title

• G06F2212/1024

  Latency reduction · CPC title

• G06F13/4013 Primary

  with data re-ordering, e.g. Endian conversion · CPC title