Reconfigurable amplifier

Patent metadata

Field	Value
Publication number	US-12009850-B2
Application number	US-202318317011-A
Country	US
Kind code	B2
Filing date	May 12, 2023
Priority date	Aug 17, 2021
Publication date	Jun 11, 2024
Grant date	Jun 11, 2024

Abstract

An amplifying circuit includes a first reconfigurable amplifier configured to selectively operate in a cascode mode or a non-cascode mode, wherein an input of the first reconfigurable amplifier is coupled to a first input of the amplifying circuit, and an output of the first reconfigurable amplifier is coupled to an output of the amplifying circuit. The amplifying circuit also includes a second reconfigurable amplifier configured to selectively operate in the cascode mode or the non-cascode mode, wherein an input of the second reconfigurable amplifier is coupled to a second input of the amplifying circuit, and an output of the second reconfigurable amplifier is coupled to the output of the amplifying circuit.

First claim

What is claimed is:

1. An apparatus, comprising:
an amplifying circuit, comprising:
a first reconfigurable amplifier configured to selectively operate in a cascode mode or a non-cascode mode, wherein an input of the first reconfigurable amplifier is coupled to a first input of the amplifying circuit, and an output of the first reconfigurable amplifier is coupled to an output of the amplifying circuit; and
a second reconfigurable amplifier configured to selectively operate in the cascode mode or the non-cascode mode, wherein an input of the second reconfigurable amplifier is coupled to a second input of the amplifying circuit, and an output of the second reconfigurable amplifier is coupled to the output of the amplifying circuit; and

a controller coupled to the first reconfigurable amplifier and the second reconfigurable amplifier, wherein the controller is configured to:
in a combining mode, cause the first reconfigurable amplifier to operate in the cascode mode and the second reconfigurable amplifier to operate in the cascode mode; and
in a first multiplexing mode, cause the first reconfigurable amplifier to operate in the non-cascode mode and turn off the second reconfigurable amplifier.

2. The apparatus of claim 1 , wherein the controller is configured to, in a second multiplexing mode, cause the second reconfigurable amplifier to operate in the non-cascode mode and turn off the first reconfigurable amplifier.

3. The apparatus of claim 1 , further comprising:
a first mixer coupled to the output of the amplifying circuit; and
a second mixer coupled to the output of the amplifying circuit.

4. The apparatus of claim 1 , wherein the first reconfigurable amplifier comprises:
a first transistor having a gate coupled to the input of the first reconfigurable amplifier, and a source coupled to a ground;
a second transistor having a source coupled to a drain of the first transistor, and a drain coupled to the output of the first reconfigurable amplifier;
a first load coupled to the output of the first reconfigurable amplifier; and
a first gate control circuit coupled to a gate of the second transistor, wherein the first gate control circuit is configured to:
in the cascode mode, bias the second transistor in a saturation region; and
in the non-cascode mode, bias the second transistor in a triode region.

5. The apparatus of claim 4 , wherein the first reconfigurable amplifier further comprises:
a supply control circuit, wherein the first load is coupled between the output of the first reconfigurable amplifier and the supply control circuit, and wherein the supply control circuit is configured to:
output a first supply voltage to the first load in the cascode mode; and
output a second supply voltage to the first load in the non-cascode mode, wherein the first supply voltage is higher than the second supply voltage.

6. The apparatus of claim 4 , wherein the second reconfigurable amplifier comprises:
a third transistor having a gate coupled to the input of the second reconfigurable amplifier, and a source coupled to the ground;
a fourth transistor having a source coupled to a drain of the third transistor, and a drain coupled to the output of the second reconfigurable amplifier;
a second load coupled to the output of the second reconfigurable amplifier; and
a second gate control circuit coupled to a gate of the fourth transistor, wherein the second gate control circuit is configured to:
in the cascode mode, bias the fourth transistor in the saturation region; and
in the non-cascode mode, bias the fourth transistor in the triode region.

7. A method of amplification using a first reconfigurable amplifier and a second reconfigurable amplifier, wherein each of the first reconfigurable amplifier and the second reconfigurable amplifier is configured to selectively operate in a cascode mode or a non-cascode mode, the method comprising:
in a combining mode,
amplifying a first signal using the first reconfigurable amplifier operating in the cascode mode to obtain an amplified first signal;
amplifying a second signal using the second reconfigurable amplifier operating in the cascode mode to obtain an amplified second signal; and
combining the amplified first signal and the amplified second signal; and

in a first multiplexing mode;
turning off the second reconfigurable amplifier; and
amplifying the first signal using the first reconfigurable amplifier operating in the non-cascode mode to obtain the amplified first signal.

8. The method of claim 7 , further comprising:
in a second multiplexing mode,
turning off the first reconfigurable amplifier; and
amplifying the second signal using second reconfigurable amplifier operating in the non-cascode mode to obtain the amplified second signal.

Assignees

• Qualcomm Inc

Inventors

• Sankaranarayanan Janakiram
• Tan Jun
• Leung Lai Kan
• Gathman Timothy Donald
• Ipek Mehmet
• Choksi Ojas

Classifications

• H03F2203/7227

  the gated amplifier being switched on or off by a switch in the supply circuit of the amplifier · CPC title

• H03F2203/30117

  the push circuit of the SEPP amplifier being a cascode circuit · CPC title

• H03F2203/30084

  the pull circuit of the SEPP amplifier being a cascode circuit · CPC title

• H03F2200/519

  the bias or supply voltage or current of the drain side of a FET amplifier being controlled to be on or off by a switch · CPC title

• H03F2200/511

  Many discrete supply voltages or currents or voltage levels can be chosen by a control signal in an IC-block amplifier circuit · CPC title