Timing skew mismatch calibration for time interleaved analog to digital converters

Patent metadata

Field	Value
Publication number	US-12009830-B2
Application number	US-202218075977-A
Country	US
Kind code	B2
Filing date	Dec 6, 2022
Priority date	Jun 24, 2020
Publication date	Jun 11, 2024
Grant date	Jun 11, 2024

Abstract

A time-interleaved analog to digital converter (TI-ADC) includes a first sub-ADC configured to sample and convert an input analog signal to generate a first digital signal and a second sub-ADC configured to sample and convert said input analog signal to generate a second digital signal. Sampling by the second sub-ADC occurs with a time skew mismatch. A multiplexor interleaves the first and second digital signals to generate a third digital signal. A time skew mismatch error determination circuit processes the first and second digital signals to generate a time error corresponding to the time skew mismatch. A slope value of said third digital signal is determined and multiplied by the time error to generate a signal error. The signal error is summed with the third digital signal to generate a digital output signal which eliminates the error due to the time skew mismatch. This correction is performed in real time.

First claim

What is claimed is:

1. A time-interleaved analog to digital converter (TI-ADC), comprising:
a first sub-ADC configured to sample and convert an input analog signal to generate a first digital signal;
a second sub-ADC configured to sample and convert said input analog signal to generate a second digital signal, wherein sampling by said second sub-ADC occurs with a time skew mismatch;
a multiplexor configured to interleave the first and second digital signals to generate a third digital signal;
a processing circuit configured to generate from the first and second digital signals an error signal that estimates an error due to said time skew mismatch; and
a summation circuit configured to sum the error signal with the third digital signal to generate a digital output signal.

2. The TI-ADC of claim 1 , wherein the processing circuit is configured to determine a slope value of said third digital signal and generate said error signal from the slope value.

3. The TI-ADC of claim 2 , wherein the processing circuit comprises:
a time skew mismatch error (TSME) determination circuit configured to process the first and second digital signals to generate a time error corresponding to said time skew mismatch; and
a multiplication circuit configured to multiply the time error by the slope value to generate said error signal.

4. The TI-ADC of claim 1 , wherein the first and second sub-ADCs each sample at a sub-sample rate of a converter sample rate, but sample with a phase offset that is a function of a number of sub-ADCs which are included in the TI-ADC.

5. The TI-ADC of claim 4 , wherein the multiplexor interleaves the first and second digital signals at the converter sample rate.

6. The TI-ADC of claim 1 , wherein the processing circuit comprises:
an interpolation circuit configured to generate a plurality of interpolated samples from the first digital signal;
a comparison circuit configured to compare the plurality of interpolated samples to the second digital signal and identify certain interpolated samples of said plurality of interpolated samples closest to the second digital signal; and
a conversion circuit configured to generate a time error corresponding to said time skew mismatch from said identified certain interpolated samples.

7. The TI-ADC of claim 6 , wherein the interpolation circuit comprises:
an upsampling circuit configured to upsample the first digital signal; and
a filtering circuit configured to filter the upsampled the first digital signal to generate the plurality of interpolated samples.

8. The TI-ADC of claim 7 , wherein the filtering circuit is a polyphase circuit, and wherein the polyphase circuit is configured to generate the plurality of interpolated samples to include a limited number of interpolated samples located around a time of the second digital signal.

9. The TI-ADC of claim 8 , wherein the limited number is substantially smaller than a rate of the upsampling.

10. The TI-ADC of claim 6 , further comprising a multiplication circuit configured to multiply the time error by a slope value of said third digital signal to generate said error signal.

11. The TI-ADC of claim 1 , wherein the error signal provides a first order estimation of the error in the second digital signal due to the time skew mismatch.

12. A method for time-interleaved analog to digital conversion, comprising:
sampling and converting an input analog signal to generate a first digital signal;
sampling and converting said input analog signal to generate a second digital signal, wherein sampling by said second sub-ADC occurs with a time skew mismatch;
interleaved selecting of the first and second digital signals to generate a third digital signal;
processing the first and second digital signals to generate an error signal that estimates an error due to the time skew mismatch; and
summing the error signal with the third digital signal to generate a digital output signal.

13. The method of claim 12 , wherein processing comprises:
determining a slope value of said third digital signal; and
generating said error signal from the slope value.

14. The method of claim 13 , wherein generating comprises:
processing the first and second digital signals to generate a time error corresponding to said time skew mismatch; and
multiplying the time error by the slope value to generate said error signal.

15. The method of claim 12 , further comprising:
generating a plurality of interpolated samples from the first digital signal;
comparing the plurality of interpolated samples to the second digital signal;
identifying certain interpolated samples of said plurality of interpolated samples closest to the second digital signal; and
generating a time error corresponding to said time skew mismatch from said identified number of interpolated samples.

16. The method of claim 15 , wherein generating the plurality of interpolated samples comprises:
upsampling the first digital signal; and
filtering the upsampled the first digital signal to generate the plurality of interpolated samples.

17. The method of claim 16 , wherein filtering comprises performing a polyphase filtering to generate the plurality of interpolated samples to include a limited number of interpolated samples located around the time of the second digital signal.

18. The method of claim 17 , wherein the limited number is substantially smaller than a rate of the upsampling.

19. The method of claim 15 , further comprising a multiplication circuit configured to multiply the time error by a slope value of said third digital signal to generate said error signal.

20. The method of claim 12 , wherein sampling of the input signal to produce the first and second digital signals occurs with a phase offset.

21. The method of claim 12 , wherein interleaved selecting is made at a rate of the sampling.

22. The method of claim 12 , wherein the error signal provides a first order estimation of the error in the second digital signal due to the time skew mismatch.

Assignees

• St Microelectronics Int Nv

Inventors

• Bal Ankur
• Singh Vikram

Classifications

• H03M1/0836 Primary

  of phase error, e.g. jitter · CPC title

• H03M1/1215

  using time-division multiplexing · CPC title

• H03M1/0624

  by synchronisation · CPC title

• H03M1/1023 Primary

  Offset correction (H03M1/1019 takes precedence; removal of offset already present on the analogue input signal H03M1/1295) · CPC title