Methods and apparatus for reducing timing-skew errors in time-interleaved analog-to-digital converters

Patent metadata

Field	Value
Publication number	US-9608652-B2
Application number	US-201514948875-A
Country	US
Kind code	B2
Filing date	Nov 23, 2015
Priority date	Feb 6, 2014
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

A time-interleaved (TI) analog-to-digital converter (ADC) architecture employs a low resolution coarse ADC channel that samples an input analog signal at a Nyquist rate and facilitates background calibration of timing-skew error without interrupting normal operation to sample/convert the input signal. The coarse ADC channel provides a timing reference for multiple higher resolution TI ADC channels that respectively sample the input signal at a lower sampling rate. The coarse ADC digital output is compared to respective TI ADC digital outputs to variably adjust in time corresponding sampling clocks of the TI ADC channels so as to substantially align them with the sampling clock of the coarse ADC channel, thus reducing timing-skew error. In one example, the coarse ADC output provides the most significant bits (MSBs) of the respective TI ADC digital outputs to further improve conversion speed and reduce power consumption in these channels.

First claim

The invention claimed is:

1. An analog-to-digital converter (ADC) apparatus, comprising:
a coarse ADC to convert an input analog signal to a coarse digital output at a first sampling rate in response to a first clock signal having a first frequency, the coarse digital output constituting a timing reference for the ADC apparatus;
a plurality of time-interleaved (TI) ADCs comprising at least a first TI ADC to convert the input analog signal to a first TI digital output at a second sampling rate in response to a second clock signal having a second frequency, wherein:
the second frequency of the second clock signal is less than the first frequency of the first clock signal;
the first TI ADC is coupled to the coarse ADC so as to receive the coarse digital output;
the first TI digital output includes a plurality of most significant bits (MSBs) and a plurality of least significant bits (LSBs); and
the plurality of MSBs of the TI digital output are based on the coarse digital output; and

a timing-skew controller, coupled to at least the first TI ADC, to make a first comparison of the coarse digital output constituting the timing reference and the first TI digital output and significantly reduce a first timing-skew error between the coarse digital output and the first TI digital output based at least in part on the first comparison.

2. The apparatus of claim 1 , wherein:
the timing-skew controller, in operation of the apparatus, generates at least one first delay control signal based on the first comparison; and
the second clock signal is variably adjusted in time with respect to the first clock signal, based on the at least one first delay control signal, so as to substantially align the second clock signal and the first clock signal and thereby significantly reduce the first timing-skew error between the coarse digital output and the first TI digital output.

3. The apparatus of claim 1 , wherein in operation of the apparatus, the timing-skew controller makes the first comparison by subtracting the coarse digital output from the first TI digital output.

4. The apparatus of claim 1 , further comprising:
a first sampling switch to receive the first clock signal and to sample the input analog signal at the first sampling rate corresponding to the first frequency of the first clock signal, so as to provide a first sampled input signal to the coarse ADC, such that the coarse ADC provides the coarse digital output corresponding to the first sampled input signal; and
a plurality of additional sampling switches comprising at least a second sampling switch to receive the second clock signal and to sample the input analog signal at the second sampling rate corresponding to the second frequency of the second clock signal, so as to provide a second sampled input signal to the first TI ADC, such that the first TI ADC provides the first TI digital output corresponding to the second sampled input signal.

5. The apparatus of any of claim 1 , wherein the coarse ADC is a flash ADC.

6. The apparatus of claim 5 , wherein the flash ADC is a sampling flash ADC.

7. The apparatus of claim 2 , further comprising:
a clock generator controller, coupled to at least the timing-skew controller, to receive the at least one first delay control signal from the timing-skew controller and a master clock signal, generate the first clock signal and the second clock signal based at least in part on the master clock signal, and variably adjust the second clock signal in time, with respect to the first clock signal, based on the at least one first delay control signal.

8. The apparatus of claim 7 , wherein the clock generator controller comprises programmable delay circuitry to receive the at least one first delay control signal and to variably adjust the second clock signal in time, based on the at least one first delay control signal, to have a variable coarse delay and a variable fine delay.

9. The apparatus of claim 8 , wherein:
the at least one first delay control signal includes a coarse digital code and a fine digital code; and
the programmable delay circuitry includes:
a first inverter coupled to a first capacitor bank controlled by the coarse digital code to provide the variable coarse delay; and
a second inverter coupled to a second capacitor bank controlled by the fine digital code to provide the variable fine delay.

10. The apparatus of claim 2 , wherein in operation of the apparatus the timing-skew controller calculates a first variance of at least a portion of the first TI digital output based on the coarse digital output, and generates the at least one first delay control signal based on the first variance.

11. The apparatus of claim 10 , wherein the timing-skew controller calculates the first variance based on a difference between the first TI digital output and the coarse digital output.

12. The apparatus of claim 10 , wherein the timing-skew controller generates the at least one first delay control signal so as to minimize the first variance over a succession of first TI digital outputs and corresponding coarse digital outputs.

13. The apparatus of claim 12 , wherein the timing-skew controller comprises a plurality of counters to generate a histogram of the difference between the first TI digital output and the coarse digital output over the succession of first TI digital outputs and corresponding coarse digital outputs so as to calculate the first variance.

14. The apparatus of claim 10 , wherein:
the first TI ADC is a successive approximation register (SAR) ADC to provide the first TI digital output as an N-bit digital word including the plurality of most significant bits (MSBs) and the plurality of least significant bits (LSBs); and
the SAR ADC includes:
a first plurality of unary-weighted MSB capacitors on which the plurality of MSBs are based, each unary-weighted MSB capacitor having a same first unit capacitance; and
a second plurality of binary-weighted LSB capacitors on which the plurality of LSBs are based, wherein:
the first variance is calculated by the timing-skew controller based at least in part on successive digital values represented by the plurality of binary-weighted LSB capacitors as a function of time.

15. The apparatus of claim 14 , wherein:
the first plurality of unary-weighted MSB capacitors and the second plurality of binary-weighted LSB capacitors have a total unit capacitance of 2 N ; and
a largest unit capacitance of the second plurality of binary-weighted LSB capacitors is equal to the first unit capacitance of each of the first plurality of unary-weighted MSB capacitors.

16. The apparatus of any of claim 1 , wherein:
the plurality of TI ADCs further comprises at least a second TI ADC to convert the input analog signal to a second TI digital output in response to a third clock signal;
the apparatus further comprises a multiplexer/combiner, coupled to the plurality of TI ADCs, to receive at least the first TI digital output and the second TI digital output and to provide a multiplexed digital output corresponding to the input analog signal;
the timing-skew controller is further coupled to the second TI ADC, to make a second comparison of the coarse digital output constituting the timing reference and the second TI digital output, and generate at least one second delay control signal based on the second comparison; and
the third clock signal is variably adjusted in time with respect to the first clock signal, based on the at least one second delay control signal, so as to substantially align the third clock signal and the first clock signal and thereby significantly

Assignees

• Lee Sunghyuk
• Lee Hae-Seung
• Chandrakasan Anantha
• Massachusetts Inst Technology

Inventors

• Lee Sunghyuk
• Lee Hae-Seung
• Chandrakasan Anantha

Classifications

• H03M1/121

  Interleaved, i.e. using multiple converters or converter parts for one channel · CPC title

• H03M1/181

  in feedback mode, i.e. by determining the range to be selected from one or more previous digital output values · CPC title

• H03M1/0609 Primary

  at two points of the transfer characteristic, i.e. by adjusting two reference values, e.g. offset and gain error · CPC title

• H03M1/1245

  Details of sampling arrangements or methods · CPC title

• H03M1/123

  Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters · CPC title