Power sensing circuit

Patent metadata

Field	Value
Publication number	US-12009828-B2
Application number	US-202318143695-A
Country	US
Kind code	B2
Filing date	May 5, 2023
Priority date	Nov 8, 2019
Publication date	Jun 11, 2024
Grant date	Jun 11, 2024

Abstract

A high resolution analog to digital converter (ADC) with improved bandwidth senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. In addition, quantization noise is subtracted from the digital output signal thereby extending the operational bandwidth of the ADC. In certain examples, the operational bandwidth of the ADC extends up to 100s of kHz (e.g., 200-300 kHz), or even higher.

First claim

What is claimed is:

1. A power sensing circuit comprising:
a first analog to digital converter (ADC) operably coupled to a first terminal of a first in-line resistor via a first single line and configured to process a first digital output signal to generate a second digital output signal that is representative of a first difference between a first in-line resistor voltage of the first terminal of the first in-line resistor and a first reference voltage;
a second ADC operably coupled to a first terminal of a second in-line resistor via a second single line and configured to process a third digital output signal to generate a fourth digital output signal that is representative of a second difference between a second in-line resistor voltage of the first terminal of the second in-line resistor and a second reference voltage, and wherein:
both the first in-line resistor and the second in-line resistor have a common resistance value;
memory that stores operational instructions; and
one or more processing modules, wherein, when enabled, configured to execute the operational instructions to:
determine a first measurement resistor voltage of a first terminal of a measurement resistor and a second measurement resistor voltage of a second terminal of the measurement resistor based on the second digital output signal associated with the first ADC and the fourth digital output signal associated with the second ADC, wherein the measurement resistor operably coupled between a second terminal of the first in-line resistor and a second terminal of the second in-line resistor;
determine a measurement resistor current through the measurement resistor based on the first measurement resistor voltage, the second measurement resistor voltage, and the measurement resistor; and
determine a power delivered to a load that is operably coupled to the second terminal of the measurement resistor based on the measurement resistor current, a second in-line resistor current associated with the second in-line resistor of the second ADC, and the second measurement resistor voltage of the second terminal of the measurement resistor.

2. The power sensing circuit of claim 1 , wherein the first ADC further comprising:
a first capacitor operably coupled to the first terminal of the first in-line resistor via the first single line and configured to produce the first in-line resistor voltage of the first terminal of the first in-line resistor based on charging by the first in-line resistor current and a first digital to analog converter (DAC) output current;
a first comparator operably coupled to the first capacitor, wherein, when enabled, the first comparator configured to generate a first comparator output signal based on the first in-line resistor voltage and a first reference voltage; and
a first digital circuit operably coupled to the first comparator, wherein, when enabled, the first digital circuit configured to process the first comparator output signal to generate a first digital output signal that is representative of a first difference between the first in-line resistor voltage and the first reference voltage; and wherein:
when enabled, the one or more processing modules further configured to execute the operational instructions to process the first digital output signal to generate the second digital output signal that is representative of the first difference between the first in-line resistor voltage and the first reference voltage; and
a first N-bit digital to analog converter (DAC) operably coupled to the one or more processing modules, wherein, when enabled, the first N-bit DAC configured to generate the first DAC output current based on the second digital output signal, wherein N is a positive integer, the first DAC output current tracks the first in-line resistor current, and the first in-line resistor voltage tracks the first reference voltage.

3. The power sensing circuit of claim 2 , wherein, when enabled, the first comparator configured to:
receive the first in-line resistor voltage via a first input of the first comparator;
receive the first reference voltage via a second input of the first comparator; and
compare the first in-line resistor voltage of the first terminal to the first reference voltage to generate the first comparator output signal.

4. The power sensing circuit of claim 2 , wherein:
the first comparator includes a sigma-delta comparator; and
the first digital circuit includes a clocked flip flop.

5. The power sensing circuit of claim 2 , wherein a first digital comparator including both the first comparator and the first digital circuit, wherein when enabled, the first digital comparator operably coupled and configured to:
receive the first in-line resistor voltage of the first terminal of the first in-line resistor via a first input of the first digital comparator;
receive the first reference voltage via a second input of the first digital comparator; and
generate the first digital output signal that is representative of the first difference between the first in-line resistor voltage and the first reference voltage.

6. The power sensing circuit of claim 2 , wherein the first digital circuit includes a sample and hold circuit (S&H).

7. The power sensing circuit of claim 2 further comprising:
a first current buffer operably coupled between a first input of the first comparator associated with the first ADC and the first terminal of the first in-line resistor; and
a second current buffer operably coupled between a second input of a comparator associated with the second ADC and the first terminal of the second in-line resistor.

8. The power sensing circuit of claim 1 , wherein the second digital output signal includes a higher resolution than the first digital output signal.

9. The power sensing circuit of claim 1 , wherein the fourth digital output signal includes a higher resolution than the third digital output signal.

10. The power sensing circuit of claim 1 , wherein:
a voltage source is operably coupled and configured to supply a voltage signal to the first terminal of the measurement resistor.

11. The power sensing circuit of claim 1 , wherein the first ADC including:
a first decimation filter operably coupled to the one or more processing modules, wherein, when enabled, the first decimation filter configured to process the second digital output signal to generate another digital output signal having a lower sampling rate and a higher resolution than the second digital output signal.

12. The power sensing circuit of claim 1 , wherein the first ADC and the second ADC are implemented within an integrated circuit.

13. The power sensing circuit of claim 12 , wherein the first in-line resistor, the second in-line resistor, the measurement resistor, and the load are implemented off chip from the integrated circuit.

14. A power sensing circuit comprising:
a first analog to digital converter (ADC) operably coupled to a first terminal of a first in-line resistor via a first single line and configured to process a first digital output signal to generate a second digital output signal that is representative of a first difference between a first in-line resistor voltage of the first terminal of the first in-line resistor and a first reference voltage;
a second ADC operably coupled to a first terminal of a second in-line resistor via a second single line and configured to process a third digital output signal to generate a fourth digital output signal that is representative of a second difference between a second in-line resistor voltage of the first terminal of the second in-line resistor and a second reference volta

Assignees

• Sigmasense Llc

Inventors

• Huynh Phuong

Classifications

• H03M3/462

  Details relating to the decimation process (decimation filters in general H03H17/0416, H03H17/0621) · CPC title

• H03M3/476 Primary

  Non-linear conversion systems · CPC title

• H03M3/422

  having one quantiser only · CPC title

• H03M1/34

  Analogue value compared with reference values (H03M1/48 takes precedence) · CPC title

• H03M1/0854

  of quantisation noise · CPC title