Multi-dielectric gate stack for crystalline thin film transistors

Patent metadata

Field	Value
Publication number	US-12009433-B2
Application number	US-201816001837-A
Country	US
Kind code	B2
Filing date	Jun 6, 2018
Priority date	Jun 6, 2018
Publication date	Jun 11, 2024
Grant date	Jun 11, 2024

Abstract

Embodiments disclosed herein include thin film transistors and methods of forming such thin film transistors. In an embodiment, the thin film transistor may comprise a substrate, a gate electrode over the substrate, and a gate dielectric stack over the gate electrode. In an embodiment, the gate dielectric stack may comprise a plurality of layers. In an embodiment, the plurality of layers may comprise an amorphous layer. In an embodiment, the thin film transistor may also comprise a semiconductor layer over the gate dielectric. In an embodiment, the semiconductor layer is a crystalline semiconductor layer. In an embodiment, the thin film transistor may also comprise a source electrode and a drain electrode.

First claim

What is claimed is:

1. A thin film transistor, comprising:
a substrate;
a gate electrode over the substrate;
a gate dielectric stack over the gate electrode, wherein the gate dielectric stack comprises a plurality of layers, the plurality of layers comprising a first layer of 1, 2, 11, 12, 14, 18, 20, and 22, a layer of Al 2 O 3 on the first layer of HfO 2 , and a second layer of HfO 2 on the layer of Al 2 O 3 , wherein a first one of the plurality of layers has a first thickness, and a second one of the plurality of layers has a second thickness different than the first thickness;
a semiconductor layer over the gate dielectric stack, wherein the semiconductor layer comprises a crystalline semiconductor layer in direct contact with the second layer of HfO 2 of the gate dielectric stack; and
a source electrode and a drain electrode, both the source electrode and the drain electrode directly on and in contact with the crystalline semiconductor layer, wherein the gate electrode extends laterally at least as wide as the semiconductor layer and at least as wide as the gate dielectric stack.

2. The thin film transistor of claim 1 , wherein an uppermost layer of the gate dielectric stack is amorphous.

3. The thin film transistor of claim 1 , wherein a thickness of each of the plurality of layers of the gate dielectric stack is less than 10 nm.

4. The thin film transistor of claim 3 , wherein a thickness of each of the plurality of layers of the gate dielectric stack is less than 5 nm.

5. A method of forming a thin film transistor, comprising:
forming a gate electrode over a substrate;
forming a gate dielectric stack over the gate electrode, wherein the gate dielectric stack comprises a first layer of HfO 2 in direct contact with the gate electrode, a layer of Al 2 O 3 on the first layer of HfO 2 , and a second layer of HfO 2 on the layer of Al 2 O 3 , and wherein a first layer of the gate dielectric stack has a first thickness, and a second layer of the dielectric stack has a second thickness different than the first thickness;
forming a semiconductor layer over the gate dielectric stack, wherein the semiconductor layer comprises a crystalline semiconductor layer in direct contact with the second layer of HfO 2 of the gate dielectric stack; and
forming a source electrode and a drain electrode directly on the crystalline semiconductor layer, wherein the gate electrode extends laterally at least as wide as the semiconductor layer and at least as wide as the gate dielectric stack.

6. The method of claim 5 , wherein the gate dielectric stack is formed with an atomic layer deposition (ALD) process.

7. The method of claim 5 , wherein each of the dielectric layers has a thickness less than 10 nm.

8. A computing device, comprising:
an integrated circuit die, wherein the integrated circuit die comprises a thin film transistor, wherein the thin film transistor comprises:
a substrate;
a gate electrode over the substrate;
an amorphous gate dielectric over the gate electrode, wherein the amorphous gate dielectric comprises a plurality of layers, the plurality of layers comprising a first layer of HfO 2 in direct contact with the gate electrode, a layer of Al 2 O 3 on the first layer of HfO 2 , and a second layer of HfO 2 on the layer of Al 2 O 3 , and wherein a first layer of the amorphous gate dielectric has a first thickness, and a second layer of the amorphous gate dielectric has a second thickness different than the first thickness;
a crystalline semiconductor layer over and in direct contact with the second layer of HfO 2 of the amorphous gate dielectric; and
a source electrode and a drain electrode, both the source electrode and the drain electrode directly on and in contact with the crystalline semiconductor layer, wherein the gate electrode extends laterally at least as wide as the semiconductor layer and at least as wide as the amorphous gate dielectric.

Assignees

• Intel Corp

Inventors

• Le Van H
• Meric Inanc
• Dewey Gilbert
• Ma Sean
• Sharma Abhishek A
• Reshotko Miriam
• Shivaraman Shriram
• Millard Kent
• Metz Matthew V
• Melitz Wilhelm
• Chu-Kung Benjamin
• Kavalieros Jack

Classifications

• H10D64/01342

  by deposition, e.g. evaporation, ALD or laser deposition (H10D64/01344 takes precedence) · CPC title

• H10D64/013 Primary

  of electrodes having a conductor capacitively coupled to a semiconductor by an insulator · CPC title

• H10D30/0312

  characterised by the gate electrodes · CPC title

• H10D30/0321

  comprising silicon, e.g. amorphous silicon or polysilicon · CPC title

• H10D62/115

  Dielectric isolations, e.g. air gaps · CPC title