Control of warpage using ABF GC cavity for embedded die package

Patent metadata

Field	Value
Publication number	US-12009318-B2
Application number	US-202217714944-A
Country	US
Kind code	B2
Filing date	Apr 6, 2022
Priority date	Sep 19, 2014
Publication date	Jun 11, 2024
Grant date	Jun 11, 2024

Abstract

Embodiments include semiconductor device packages and methods of forming such packages. In an embodiment, the package may include a die-side reinforcement layer with a cavity formed through the die-side reinforcement layer. A die having a first side and an opposite second side comprising a device side may be positioned in the cavity with the first side of the die being substantially coplanar with a first side of the die-side reinforcement layer. In an embodiment, a build-up structure may be coupled to a second side of the die. Embodiments include a build-up structure that includes a plurality of alternating layers of patterned conductive material and insulating material.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a die having a first side and a second side opposite the first side, and the die having a first lateral sidewall and a second lateral sidewall;
a plurality of conductive contacts at the second side of the die; a reinforcement layer having a first portion laterally adjacent to and in contact with the first lateral sidewall of the die, the reinforcement layer having a second portion laterally adjacent to and in contact with the second lateral sidewall of the die, and the reinforcement layer having a thickness less than a thickness of the die;
a dielectric material on and in direct physical contact with the second side of the die and on the surface of the reinforcement layer; a first conductive via through the dielectric material, the first conductive via coupled to a first of the plurality of conductive contacts;
a second conductive via through the dielectric material, the second conductive via coupled to a second of the plurality of conductive contacts;
a first conductive trace on the dielectric material, the first conductive trace in contact with the first conductive via;
a second conductive trace on the dielectric material, the second conductive trace in contact with the second conductive via; a first solder bump coupled to the first conductive trace, the first solder bump outside of a periphery of the die and inside a periphery of the reinforcement layer, wherein the first conductive trace extends from inside the periphery of the die to a location vertically over the first solder bump; and a second solder bump coupled to the second conductive trace, the second solder bump outside of the periphery of the die and inside the periphery of the reinforcement layer, wherein the second conductive trace extends from inside the periphery of the die to a location vertically over the second solder bump, and wherein there are no solder bumps inside of the periphery of the die.

2. The semiconductor package of claim 1 , wherein the reinforcement layer has a CTE less than a CTE of the dielectric material.

3. The semiconductor package of claim 1 , wherein the reinforcement layer has a surface co-planar with the second side of the die.

4. The semiconductor package of claim 1 , wherein the reinforcement layer has a surface above the first side of the die.

5. The semiconductor package of claim 1 , further comprising a die attach film on the first side of the die.

6. The semiconductor package of claim 1 , wherein the reinforcement layer completely laterally surrounds the die.

7. The semiconductor package of claim 1 , wherein the first solder bump is coupled to the first conductive trace by a third conductive trace.

8. The semiconductor package of claim 6 , wherein the second solder bump is coupled to the second conductive trace by a fourth conductive trace.

9. A semiconductor package, comprising:
a die having a first side and a second side opposite the first side, the die having a first lateral sidewall and a second lateral sidewall, and the die having electronic circuitry on the second side of the die;
a plurality of conductive contacts electrically coupled to the electronic circuitry of the die;
a reinforcement layer having a first portion laterally adjacent to and in contact with the first lateral sidewall of the die, the reinforcement layer having a second portion laterally adjacent to and in contact with the second lateral sidewall of the die, and the reinforcement layer having a thickness less than a thickness of the die;
a dielectric material on and in direct physical contact with the second side of the die and on the surface of the reinforcement layer;
a first conductive via through the dielectric material, the first conductive via coupled to a first of the plurality of conductive contacts; a second conductive via through the dielectric material, the second conductive via coupled to a second of the plurality of conductive contacts; a first conductive trace on the dielectric material, the first conductive trace in contact with the first conductive via;
a second conductive trace on the dielectric material, the second conductive trace in contact with the second conductive via; a first solder bump coupled to the first conductive trace, the first solder bump outside of a periphery of the die and inside a periphery of the reinforcement layer, wherein the first conductive trace extends from inside the periphery of the die to a location vertically over the first solder bump; and a second solder bump coupled to the second conductive trace, the second solder bump outside of the periphery of the die and inside the periphery of the reinforcement layer, wherein the second conductive trace extends from inside the periphery of the die to a location vertically over the second solder bump, and wherein there are no solder bumps inside of the periphery of the die.

10. The semiconductor package of claim 9 , wherein the reinforcement layer has a CTE less than a CTE of the dielectric material.

11. The semiconductor package of claim 9 , wherein the reinforcement layer has a surface co-planar with the second side of the die.

12. The semiconductor package of claim 9 , wherein the reinforcement layer has a surface above the first side of the die.

13. The semiconductor package of claim 9 , further comprising a die attach film on the first side of the die.

14. The semiconductor package of claim 9 , wherein the reinforcement layer completely laterally surrounds the die.

15. The semiconductor package of claim 9 , wherein the first solder bump is coupled to the first conductive trace by a third conductive trace.

16. The semiconductor package of claim 15 , wherein the second solder bump is coupled to the second conductive trace by a fourth conductive trace.

17. A semiconductor package, comprising:
a die having a first side and a second side opposite the first side, and the die having a first lateral sidewall and a second lateral sidewall;
a plurality of conductive contacts at the second side of the die;
a reinforcement layer having a first portion laterally adjacent to and in contact with the first lateral sidewall of the die, the reinforcement layer having a second portion laterally adjacent to and in contact with the second lateral sidewall of the die, and the reinforcement layer having a thickness less than a thickness of the die;
a dielectric material on and in direct physical contact with the second side of the die and on the surface of the reinforcement layer; a first conductive via through the dielectric material, the first conductive via coupled to a first of the plurality of conductive contacts;
a second conductive via through the dielectric material, the second conductive via coupled to a second of the plurality of conductive contacts;
a first conductive trace on the dielectric material, the first conductive trace in contact with the first conductive via;
a second conductive trace on the dielectric material, the second conductive trace in contact with the second conductive via;
a first solder bump electrically coupled to the first conductive trace, the first solder bump outside of a periphery of the die and inside a periphery of the reinforcement layer, wherein the first conductive trace extends from inside the periphery of the die to a location vertically over the first solder bump; and a second solder bump electrically coupled to the second conductive trace, the second solder bump outside of the periphery of the die and inside the periphery of the reinforcement layer, wherein the second conductive trace extends from inside the periphery o

Assignees

• Intel Corp

Inventors

• Raorane Digvijay A
• Chin Ian En Yoon
• Sobieski Daniel N

Classifications

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W74/114

  by a substrate and the encapsulations · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title

• H10W95/00

  Packaging processes not covered by the other groups of this subclass · CPC title