Semiconductor device and method of forming supporting layer over semiconductor die in thin fan-out wafer level chip scale package

Patent metadata

Field	Value
Publication number	US-9385102-B2
Application number	US-201213630912-A
Country	US
Kind code	B2
Filing date	Sep 28, 2012
Priority date	Sep 28, 2012
Publication date	Jul 5, 2016
Grant date	Jul 5, 2016

Abstract

A semiconductor device includes a semiconductor die. An encapsulant is formed around the semiconductor die. A build-up interconnect structure is formed over a first surface of the semiconductor die and encapsulant. A first supporting layer is formed over a second surface of the semiconductor die as a supporting substrate or silicon wafer disposed opposite the build-up interconnect structure. A second supporting layer is formed over the first supporting layer an includes a fiber enhanced polymer composite material comprising a footprint including an area greater than or equal to an area of a footprint of the semiconductor die. The semiconductor die comprises a thickness less than 450 micrometers (μm). The thickness of the semiconductor die is at least 1 μm less than a difference between a total thickness of the semiconductor device and a thickness of the build-up interconnect structure and the second supporting layer.

First claim

What is claimed:

1. A method of making a semiconductor device, comprising:
providing a semiconductor die;
forming a first supporting layer over the semiconductor die;
forming an encapsulant around the semiconductor die and over a side surface of the first supporting layer; and
forming an interconnect structure over the semiconductor die and encapsulant opposite the first supporting layer, wherein a surface of the encapsulant opposite the interconnect structure is devoid of the first supporting layer.

2. The method of claim 1 , further including forming the first supporting layer including a footprint comprising an area equal to an area of a footprint of the semiconductor die.

3. The method of claim 1 , further including forming the first supporting layer including a footprint comprising an area greater than an area of a footprint of the semiconductor die.

4. The method of claim 1 , further including forming the first supporting layer as a warpage balance layer comprising a coefficient of thermal expansion in a range of 10-300 ppm/K.

5. A method of making a semiconductor device, comprising:
providing a semiconductor die;
forming an interconnect structure over the semiconductor die;
forming a first supporting layer over the semiconductor die opposite the interconnect structure, the first supporting layer including a footprint comprising an area less than an area of a footprint of the interconnect structure; and
forming a second supporting layer in a peripheral area around the semiconductor die extending a distance of at least 50 micrometers.

6. The method of claim 5 , wherein the area of the footprint of the first supporting layer is greater than an area of a footprint of the semiconductor die.

7. The method of claim 6 , further including forming an opening through the first supporting layer outside the footprint of the semiconductor die.

8. The method of claim 5 , further including forming a marking layer over the first supporting layer.

9. A semiconductor device, comprising:
a semiconductor die;
an encapsulant formed around the semiconductor die;
an interconnect structure formed over the semiconductor die and encapsulant;
a first supporting layer including a footprint comprising an area greater than or equal to an area of a footprint of the semiconductor die formed over the semiconductor die opposite the interconnect structure; and
a second supporting layer including a fiber material formed over the first supporting layer.

10. The semiconductor device of claim 9 , wherein the first supporting layer includes a core material formed of epoxy and glass fibers comprising a coefficient of thermal expansion in a range of 4-150 ppm/K.

11. The semiconductor device of claim 10 , wherein the first supporting layer includes openings formed through the first supporting layer outside the footprint of the semiconductor die.

12. The semiconductor device of claim 9 , further including a marking layer formed over the first supporting layer.

13. A semiconductor device comprising:
a semiconductor die;
an encapsulant formed around the semiconductor die;
an interconnect structure formed over the semiconductor die and encapsulant;
a first supporting layer including a footprint comprising an area greater than or equal to an area of a footprint of the semiconductor die formed over the semiconductor die opposite the interconnect structure; and
a second supporting layer embedded within the semiconductor device at a peripheral area around the semiconductor die that extends within the semiconductor device a distance of at least 50 micrometers.

14. The semiconductor device of claim 13 , wherein the area of the footprint of the first supporting layer is equal to the area of the footprint of the semiconductor die.

15. A semiconductor device, comprising:
a semiconductor die;
an interconnect structure formed over the semiconductor die;
a first supporting layer formed over the semiconductor die opposite the interconnect structure; and
an encapsulant formed around the semiconductor die and over a side surface of the first supporting layer, wherein a surface of the encapsulant opposite the interconnect structure is devoid of the first supporting layer.

16. The semiconductor device of claim 15 , further including a second supporting layer embedded within the encapsulant at a peripheral area around the semiconductor die that extends within the semiconductor device a distance of at least 50 micrometers.

17. The semiconductor device of claim 15 , wherein the first supporting layer includes a footprint comprising an area equal to an area of a footprint of the semiconductor die.

18. The semiconductor device of claim 15 , wherein the first supporting layer includes a footprint comprising an area greater than an area of a footprint of the semiconductor die.

19. The semiconductor device of claim 18 , wherein the first supporting layer includes openings formed through the first supporting layer outside the footprint of the semiconductor die.

20. The semiconductor device of claim 18 , wherein the first supporting layer includes properties selected to control warpage of the semiconductor device.

21. The semiconductor device of claim 18 , further including a marking layer formed over the first supporting layer.

22. A semiconductor device, comprising:
a semiconductor die;
an interconnect structure formed over the semiconductor die;
a first supporting layer formed over the semiconductor die opposite the interconnect structure, the first supporting layer including a footprint comprising an area less than an area of a footprint of the interconnect structure; and
a second supporting layer embedded within the semiconductor device at a peripheral area around the semiconductor die that extends within the semiconductor device a distance of at least 50 micrometers.

23. The semiconductor device of claim 22 , wherein the area of the footprint of the first supporting layer is equal to an area of a footprint of the semiconductor die.

24. The semiconductor device of claim 22 , wherein the area of the footprint of the first supporting layer is greater than an area of a footprint of the semiconductor die.

25. The semiconductor device of claim 24 , wherein the first supporting layer includes openings formed through the first supporting layer outside the footprint of the semiconductor die.

26. The semiconductor device of claim 24 , wherein the first supporting layer includes properties selected to control warpage of the semiconductor device.

27. The semiconductor device of claim 24 , further including a marking layer formed over the first supporting layer.

Assignees

• Stats Chippac Ltd
• Stats Chippac Pte Ltd

Inventors

• Lin Yaojian
• Chen Kang
• GU Yu

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title