Display panel and electronic apparatus

Patent metadata

Field	Value
Publication number	US-12004382-B2
Application number	US-202117158972-A
Country	US
Kind code	B2
Filing date	Jan 26, 2021
Priority date	Jun 1, 2020
Publication date	Jun 4, 2024
Grant date	Jun 4, 2024

Abstract

A display panel includes a substrate, two pixels arranged on the substrate and spaced from each other with a transmission area therebetween, and a blocking layer between the substrate and the two pixels, the blocking layer including an opening corresponding to the transmission area. An edge of the opening includes a plurality of convex portions.

First claim

What is claimed is:

1. A display panel comprising:
a substrate;
two pixels on the substrate and spaced from each other with a transmission area therebetween; and
a blocking layer between the substrate and the two pixels, the blocking layer defining an opening corresponding to the transmission area,
wherein an edge of the opening comprises a plurality of convex portions.

2. The display panel of claim 1 , wherein a width of each of the plurality of convex portions is less than or equal to 10% of a width of the opening.

3. The display panel of claim 2 , wherein the width of each of the plurality of convex portions is 5% to 10% of the width of the opening.

4. The display panel of claim 1 , wherein each of the plurality of convex portions is semi-circular, semi-elliptical, triangular, or quadrangular.

5. The display panel of claim 1 , wherein each of the two pixels comprises a light-emitting diode, and
wherein each of the light-emitting diodes is electrically connected to a pixel circuit comprising a transistor and a capacitor.

6. The display panel of claim 5 , wherein the blocking layer is between the substrate and the pixel circuit.

7. The display panel of claim 1 , wherein the opening of the blocking layer is symmetrical with respect to a virtual first axis passing through a center of the opening and extending in a first direction.

8. The display panel of claim 7 , wherein the opening of the blocking layer is symmetrical with respect to a virtual second axis passing through the center of the opening and extending in a second direction intersecting the first direction.

9. The display panel of claim 7 , wherein the opening of the blocking layer comprises:
a first portion and a second portion arranged along the first direction and located at respective sides of the opening with the center of the opening therebetween; and
a third portion and a fourth portion arranged along a second direction intersecting the first direction and located at respective sides of the opening with the center of the opening therebetween.

10. A display panel comprising:
a substrate;
two pixels on the substrate and spaced from each other with a transmission area therebetween; and
a blocking layer between the substrate and the two pixels, the blocking layer defining an opening corresponding to the transmission area,
wherein an edge of the opening comprises a plurality of convex portions,
wherein the opening of the blocking layer is symmetrical with respect to a virtual first axis passing through a center of the opening and extending in a first direction,
wherein the opening of the blocking layer comprises:
a first portion and a second portion arranged along the first direction and located at respective sides of the opening with the center of the opening therebetween; and
a third portion and a fourth portion arranged along a second direction intersecting the first direction and located at respective sides of the opening with the center of the opening therebetween, and

wherein an edge of the first portion, an edge of the second portion, an edge of the third portion, and an edge of the fourth portion each comprise different ones of the plurality of convex portions.

Assignees

• Samsung Display Co Ltd

Inventors

• Chae Jongwon
• Ko Moosoon
• Son Sewan
• Choi Kyunghyun

Classifications

• H10H29/142

  Two-dimensional arrangements, e.g. asymmetric LED layout · CPC title

• H10K59/126 Primary

  Shielding, e.g. light-blocking means over the TFTs · CPC title

• H10K59/131

  Interconnections, e.g. wiring lines or terminals · CPC title

• H10K59/353 Primary

  characterised by the geometrical arrangement of the RGB subpixels · CPC title

• H10K59/40 Primary

  OLEDs integrated with touch screens · CPC title