Wiring board and production method for same

US12004305B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12004305-B2
Application numberUS-201917415041-A
CountryUS
Kind codeB2
Filing dateDec 19, 2019
Priority dateDec 20, 2018
Publication dateJun 4, 2024
Grant dateJun 4, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A wiring board according to the present disclosure includes a first insulating material layer having a surface with an arithmetic average roughness Ra of 100 nm or less, a metal wiring provided on the surface of the first insulating material layer, and a second insulating material layer provided to cover the metal wiring, in which the metal wiring is configured by a metal layer in contact with the surface of the first insulating material layer and a conductive part stacked on a surface of the metal layer, and a nickel content rate of the metal layer is 0.25 to 20% by mass.

First claim

Opening claim text (preview).

The invention claimed is: 1. A method for manufacturing a wiring board, the method comprising, in a following order: (a) a step of adsorbing an electroless plating catalyst to a first insulating material layer; (b) a step of forming a metal layer on a surface of the first insulating material layer by electroless plating; (c) a step of forming a resist having an opening for wiring pattern formation on a surface of the metal layer; and (d) a step of forming a conductive part in a region, which is the surface of the metal layer and is exposed from the resist, by electrolytic plating, wherein an arithmetic average roughness Ra of the surface of the first insulating material layer is 100 nm or less, and a nickel content rate of the metal layer is 0.25 to 20% by mass. 2. The method for manufacturing a wiring board according to claim 1 , wherein in the step (b), the metal layer is formed using an electroless copper-nickel-phosphorus plating solution. 3. The method for manufacturing a wiring board according to claim 1 , wherein the surface of the first insulating material layer is not subjected to a roughening treatment with a desmear treatment solution, before performing the step (a). 4. The method for manufacturing a wiring board according to claim 1 , further comprising a step of performing at least one modification treatment selected from the group consisting of ultraviolet ray irradiation, electron beam irradiation, an ozone water treatment, a corona discharge treatment, and a plasma treatment with respect to the surface of the first insulating material layer, before performing the step (a). 5. The method for manufacturing a wiring board according to claim 1 , further comprising, in a following order: (e) a step of removing the resist; (f) a step of removing the metal layer exposed by a removal of the resist and the catalyst between the metal layer and the first insulating material layer; and (g) a step of forming a second insulating material layer to cover a metal wiring configured by the metal layer remaining on the first insulating material layer and the conductive part. 6. A wiring board comprising: a first insulating material layer having a surface with an arithmetic average roughness Ra of 100 nm or less; a metal wiring provided on the surface of the first insulating material layer; and a second insulating material layer provided to cover the metal wiring, wherein the metal wiring is configured by a metal layer in contact with the surface of the first insulating material layer and a conductive part stacked on a surface of the metal layer, and a nickel content rate of the metal layer is 0.25 to 20% by mass. 7. The wiring board according to claim 6 , wherein the nickel content rate of the metal layer is 3 to 20% by mass. 8. The wiring board according to claim 6 , wherein the nickel content rate of the metal layer is 0.25 to 3% by mass. 9. The wiring board according to claim 6 , wherein the first insulating material layer is composed of a cured product of a thermosetting resin composition. 10. The wiring board according to claim 6 , wherein the first insulating material layer is composed of a cured product of a photosensitive resin composition. 11. The wiring board according to claim 6 , further comprising a support substrate the first insulating layer being formed on, wherein the support substrate is wafer-shaped and has a diameter of 200 mm, 300 mm or 450 mm. 12. The wiring board according to claim 6 , further comprising a support substrate the first insulating layer being formed on, wherein the support substrate is rectangular panel-shaped and has a side of 300 to 700 mm. 13. The wiring board according to claim 6 , wherein the first insulating layer has a thermal expansion coefficient of 80×10 −6 /K or less.

Assignees

Inventors

Classifications

  • characterised by features of form at particular places, e.g. in edge regions {(non-uniform thickness B32B3/263)} · CPC title

  • characterised by added members at particular parts {(layer formed of separate pieces of material which are juxtaposed side-by-side B32B3/14, B32B3/18)} · CPC title

  • H05K3/181Primary

    by electroless plating (adhesives therefor H05K3/387) · CPC title

  • by masking · CPC title

  • Multilayered product (layered product B32B) · CPC title

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Frequently asked questions

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What does patent US12004305B2 cover?
A wiring board according to the present disclosure includes a first insulating material layer having a surface with an arithmetic average roughness Ra of 100 nm or less, a metal wiring provided on the surface of the first insulating material layer, and a second insulating material layer provided to cover the metal wiring, in which the metal wiring is configured by a metal layer in contact with …
Who is the assignee on this patent?
Showa Denko Materials Co Ltd, Resonac Corp
What technology area does this patent fall under?
Primary CPC classification H05K3/181. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jun 04 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).