Double gate transistor device and method of operating

Patent metadata

Field	Value
Publication number	US-12003231-B2
Application number	US-201916722809-A
Country	US
Kind code	B2
Filing date	Dec 20, 2019
Priority date	Feb 29, 2016
Publication date	Jun 4, 2024
Grant date	Jun 4, 2024

Abstract

In accordance with an embodiment, a method includes switching on a transistor device by generating a first conducting channel by driving a first gate electrode and, before generating the first conducting channel, generating a second conducting channel by driving a second gate electrode, wherein the second gate electrode is adjacent the first gate electrode in a current flow direction of the transistor device.

First claim

What is claimed is:

1. A transistor device comprising:
a semiconductor body with a first semiconductor layer comprising a first type of group III nitride and a second semiconductor layer adjoining the first semiconductor layer and comprising a second type of group III nitride;
a source electrode having a vertical edge immediately adjacent to a first vertical edge of the first semiconductor layer and immediately adjacent to a first vertical edge of the second semiconductor layer in a vertical cross-sectional view;
a drain electrode spaced apart from the source electrode and having a vertical edge immediately adjacent to a second vertical edge of the first semiconductor layer and immediately adjacent to a second vertical edge of the second semiconductor layer in a vertical cross-sectional view; and
a first gate electrode configured for generating a first conducting channel in the semiconductor body in response to a first signal driving the first gate electrode at a first slew rate and a second gate electrode configured for generating a second conducting channel in the semiconductor body in response to a second signal driving the second gate electrode at a second slew rate greater than the first slew rate, wherein the first gate electrode and the second gate electrode are spaced apart in a current flow direction of the transistor device,
wherein the first gate electrode and the second gate electrode are electrically insulated with respect to each other, and wherein the first gate electrode and the second gate electrode are controlled individually with respect to each other in a mode of operation,
wherein each of the first gate electrode and the second gate electrode extends through the second semiconductor layer into the first semiconductor layer and is dielectrically insulated from the second semiconductor layer and the first semiconductor layer by a gate dielectric.

2. The transistor device of claim 1 , wherein the semiconductor body further comprises a third semiconductor layer adjoining the second semiconductor layer and comprising a group III nitride, and wherein each of the first gate electrode and the second gate electrode further extends through the third semiconductor layer and is further dielectrically insulated from the third semiconductor layer by the gate dielectric.

3. The transistor device of claim 1 , wherein each of the first semiconductor layer and the second semiconductor layer comprises a doped semiconductor layer.

4. The transistor device of claim 1 , wherein each of the first semiconductor layer and the second semiconductor layer comprises an intrinsic semiconductor layer.

5. The transistor device of claim 4 , wherein the semiconductor body further comprises at least one third semiconductor layer adjoining the second semiconductor layer and comprising a doped group III nitride, and wherein each of the first gate electrode and the second gate electrode further extends through the at least one third semiconductor layer and is further dielectrically insulated from the at least one third semiconductor layer by the gate dielectric.

6. The transistor device of claim 1 , further comprising a field electrode adjoining the second gate electrode.

7. The transistor device of claim 1 , wherein the second gate electrode is electrically connected with the source electrode.

8. The transistor device of claim 1 , wherein the first type of group III nitride comprises gallium nitride (GaN), and wherein the second type of group III nitride comprises aluminum gallium nitride (AlGaN).

9. A method of using a transistor device, the method comprising:
with a first gate electrode of the transistor device, generating a first conducting channel in a semiconductor body in response to a first signal driving the first gate electrode at a first slew rate, wherein the semiconductor body has a first semiconductor layer comprising a first type of group III nitride and a second semiconductor layer adjoining the first semiconductor layer and comprising a second type of group III nitride; and
with a second gate electrode of the transistor device, generating a second conducting channel in the semiconductor body in response to a second signal driving the second gate electrode at a second slew rate greater than the first slew rate, wherein the first gate electrode and the second gate electrode are spaced apart in a current flow direction of the transistor device,
wherein the first gate electrode and the second gate electrode are electrically insulated with respect to each other, and wherein the first gate electrode and the second gate electrode are controlled individually with respect to each other in a mode of operation,
wherein each of the first gate electrode and the second gate electrode extends through the second semiconductor layer into the first semiconductor layer and is dielectrically insulated from the second semiconductor layer and the first semiconductor layer by a gate dielectric,
wherein, in a vertical cross-sectional view, a source electrode has a vertical edge immediately adjacent to a first vertical edge of the first semiconductor layer and immediately adjacent to a first vertical edge of the second semiconductor layer, and
wherein, in a vertical cross-sectional view, a drain electrode is spaced apart from the source electrode and has a vertical edge immediately adjacent to a second vertical edge of the first semiconductor layer and immediately adjacent to a second vertical edge of the second semiconductor layer.

10. The method of claim 9 , wherein the semiconductor body further comprises a third semiconductor layer adjoining the second semiconductor layer and comprising a group III nitride, and wherein each of the first gate electrode and the second gate electrode further extends through the third semiconductor layer and is further dielectrically insulated from the third semiconductor layer by the gate dielectric.

11. The method of claim 9 , wherein each of the first semiconductor layer and the second semiconductor layer comprises a doped semiconductor layer.

12. The method of claim 9 , wherein each of the first semiconductor layer and the second semiconductor layer comprises an intrinsic semiconductor layer.

13. The method of claim 12 , wherein the semiconductor body further comprises at least one third semiconductor layer adjoining the second semiconductor layer and comprising a doped group III nitride, and wherein each of the first gate electrode and the second gate electrode further extends through the at least one third semiconductor layer and is further dielectrically insulated from the at least one third semiconductor layer by the gate dielectric.

14. The method of claim 9 , wherein a field electrode adjoins the second gate electrode.

15. A method of forming a transistor device, the method comprising:
forming a semiconductor body with a first semiconductor layer comprising a first type of group III nitride and a second semiconductor layer adjoining the first semiconductor layer and comprising a second type of group III nitride;
forming a source electrode having a vertical edge immediately adjacent to a first vertical edge of the first semiconductor layer and immediately adjacent to a first vertical edge of the second semiconductor layer in a vertical cross-sectional view;
forming a drain electrode spaced apart from the source electrode and having a vertical edge immediately adjacent to a second vertical edge of the first semiconductor layer and immediately adjacent to a second vertical edge of the second semiconductor layer in a vertical cross-sectional view; and
forming a first gate electrode configured for gene

Assignees

• Infineon Technologies Austria Ag

Inventors

• Bina Markus
• Barrenscheen Jens
• Mauder Anton

Classifications

• H10D64/256

  for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673) · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D62/343

  Gate regions of field-effect devices having PN junction gates · CPC title

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D64/117

  Recessed field plates, e.g. trench field plates or buried field plates · CPC title