High performance integrated RF passives using dual lithography process

Patent metadata

Field	Value
Publication number	US-12002745-B2
Application number	US-202117544693-A
Country	US
Kind code	B2
Filing date	Dec 7, 2021
Priority date	Dec 21, 2015
Publication date	Jun 4, 2024
Grant date	Jun 4, 2024

Abstract

Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components.

First claim

What is claimed is:

1. A capacitor in an electrical package comprising:
a first dielectric layer;
a first capacitor plate over a top surface of the first dielectric layer and along a sidewall of the first dielectric layer;
a dielectric spacer over a surface of the first capacitor plate;
a second capacitor plate separated from the first capacitor plate by the dielectric spacer layer; and
a second dielectric layer laterally adjacent to the first capacitor plate, the dielectric spacer, and the second capacitor plate, wherein the second dielectric layer has an uppermost surface at a same level as an upper surface of the second capacitor plate.

2. The capacitor of claim 1 , wherein the first and second capacitor plates are in a single routing layer of the package.

3. The capacitor of claim 2 , wherein the dielectric spacer is less than 10 μm thick.

4. The capacitor of claim 2 , wherein the first and second capacitor plates include interdigitated square meander extensions.

5. The capacitor plate of claim 4 , wherein the extensions are in three-dimensions.

Assignees

• Intel Corp

Inventors

• Elsherbini Adel A
• Manusharow Mathew J
• Bharath Krishna
• Lambert William J
• Sankman Robert L
• Aleksov Aleksandar
• Rawlings Brandon M
• Eid Feras
• Soto Gonzalez Javier
• Jiao Meizi
• Nad Suddhasattwa
• Kamgaing Telesphor

Classifications

• H10W44/241

  for passive devices or passive elements · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/095

  of vias therein · CPC title

• H10W70/05

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title