Methods and systems for component analysis, sorting, and sequencing based on component parameters and devices utilizing the methods and systems

Patent metadata

Field	Value
Publication number	US-12002720-B2
Application number	US-202017101888-A
Country	US
Kind code	B2
Filing date	Nov 23, 2020
Priority date	Nov 23, 2020
Publication date	Jun 4, 2024
Grant date	Jun 4, 2024

Abstract

A process includes measuring at least one component parameter of a plurality of components with a testing device; and arranging at least a portion of the plurality of components in a sequential order based on the at least one component parameter with an implementation system in at least one of the following: a shipping format and a device implementation of the portion of the plurality of components. A system is disclosed as well.

First claim

What is claimed is:

1. A power module, comprising:
at least one electrically conductive power substrate;
a housing arranged on the at least one electrically conductive power substrate; and
a plurality of power devices arranged on and connected to the at least one electrically conductive power substrate,
wherein each of the plurality of power devices are arranged in a sequential order based on at least one component parameter such that a variation of the at least one component parameter between adjacent pairs of the power devices in the sequential order is minimized;
wherein the plurality of power devices are configured as an array of paralleled devices on the at least one electrically conductive power substrate;
wherein the plurality of power devices comprise at least one of the following: a MEtal Semiconductor Field-Effect Transistor (MESFET), a Metal Oxide Field Effect Transistor (MOSFET), a Junction Field Effect Transistor (JFET), a Bipolar Junction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), a static induction transistor (SiT), a High-Electron-Mobility Transistor (HEMT), a metal insulator semiconductor FET (MISFET), a Thyristor, a Gate Turn-Off Thyristor (GTO), an Integrated Gate-Commutated Thyristor (IGCT), and/or a diode:
wherein the sequential order of the plurality of power devices comprises at least one of the following: an Ascending-Descending Sequencing (ADS) where the plurality of power devices are sequenced from a low value of the at least one component parameter to a high value of the at least one component parameter or a high value of the at least one component parameter to a low value of the at least one component parameter, a Half-Sine Sequencing (HSS) where the plurality of power devices are sequenced to start and end with a low value of the at least one component parameter, a Half-Sine Sequencing (HSS) where the plurality of power devices are sequenced to start and end with a high value of the at least one component parameter, and a Full-Sine Sequencing (FSS) where the plurality of power devices are sequenced to start and end with a median value of the at least one component parameter; and
wherein the at least one component parameter comprises at least one of the following for each of the plurality of power devices: a threshold voltage, an on-state resistance, a static conduction characteristic, a dynamic switching characteristic, a drain current magnitude, a transconductance, a gate threshold voltage, a gate-source leakage current, a drain-source leakage current, a drain-source on-state resistance, a total gate charge, a gate-source charge, a gate-drain charge, an input capacitance, a reverse transfer capacitance, a gate resistance, a turn-on delay time, a turn-on rise time, a turn-off delay time, a turn-off fall time, a forward voltage, a reverse recovery time, a reverse recovery charge, a turn-on drain current, a drain-source current, a gate-source voltage, a transfer function, a drain-source voltage, a pulsed drain current, a DC body diode forward current, a pulsed body diode current, a max transient voltage, a turn-off gate voltage, a power dissipation, a virtual function temperature, a body diode thermal resistance, a thermal resistance, a body diode forward voltage, a gate-source threshold voltage, a zero-gate voltage drain current, an internal gate resistance, an output capacitance, a reverse capacitance, a stored energy, a rise time, a fall time, a turn-on energy, a turn-off energy, a total switching energy, a diode reverse recovery charge, a diode peak reverse recovery current, a resistance, a capacitance, resonant points, an inductance, transfer data, parametric data, data characterizing static losses, a device transfer curve, a transfer function, data representative of an independent scalar input versus a dependent scalar output, time domain waveforms, and/or data characterizing dynamic losses.

2. The power module of claim 1 ,
wherein the plurality of power devices comprise power semiconductor devices that comprise at least one of the following: Silicon Carbide (SiC) MOSFETs, Silicon Carbide (SiC) JFETs, Silicon Carbide (SiC) IGBTs, Silicon Carbide (SiC) Schottky Diodes, and Gallium Nitride (GaN) HEMTs.

3. The power module of claim 1 ,
wherein the plurality of power devices comprise wide band gap power semiconductor devices that comprise at least one of the following: Silicon Carbide (SiC) MOSFETs, Silicon Carbide (SiC) JFETs, Silicon Carbide (SiC) IGBTs, Silicon Carbide (SiC) Schottky Diodes, and Gallium Nitride (GaN) HEMTs.

4. The power module of claim 1 ,
wherein the plurality of power devices comprise devices fabricated from wide bandgap materials that comprise at least one of the following: Gallium Nitride (GaN) and Silicon Carbide (SiC).

5. The power module of claim 1 , further comprising:
a first terminal electrically connected to the at least one electrically conductive power substrate;
a second terminal;
a third terminal electrically connected to the at least one electrically conductive power substrate; and
a base plate.

6. The power module of claim 1 , wherein the sequential order of the plurality of power devices comprises the Ascending-Descending Sequencing (ADS) where the plurality of power devices are sequenced from a low value of the at least one component parameter to a high value of the at least one component parameter or a high value of the at least one component parameter to a low value of the at least one component parameter.

7. The power module of claim 1 , wherein the sequential order of the plurality of power devices comprises the Half-Sine Sequencing (HSS) where the plurality of power devices are sequenced to start and end with a low value of the at least one component parameter.

8. The power module of claim 1 , wherein the sequential order of the plurality of power devices comprises the Half-Sine Sequencing (HSS) where the plurality of power devices are sequenced to start and end with a high value of the at least one component parameter.

9. The power module of claim 1 , wherein the sequential order of the plurality of power devices comprises the Full-Sine Sequencing (FSS) where the plurality of power devices are sequenced to start and end with a median value of the at least one component parameter.

10. A system comprising a plurality of the power modules according to claim 1 , wherein:
each of the plurality of the power modules comprise a subset of the plurality of power devices that are arranged in a sequential order based on at least one component parameter such that the sequential order of the plurality of power devices ensures that a variation of the at least one component parameter between adjacent pairs of the power devices in the sequential order is minimized; and
a variation of the at least one component parameter between the plurality of the power modules is minimized.

11. The power module of claim 1 , wherein the plurality of power devices comprise at least three power devices.

12. The power module of claim 11 , wherein the at least one component parameter comprises a plurality of the at least one component parameter for each of the plurality of power devices.

13. A power module, comprising:
at least one power substrate;
a housing arranged on the at least one power substrate; and
a plurality of power devices arranged on to the at least one power substrate,
wherein each of the plurality of power devices are arranged in a sequential order based on at least one component parameter such that a variation of the at least one component parameter between adjacent pairs of the power devices in the sequential order is minimized;
wherein the plurality of power devices

Assignees

• Cree Fayetteville Inc
• Wolfspeed Inc

Inventors

• Cole Zach
• Roddy Morgan Andrew
• Fraley John R
• Hayes Jonathan K
• Barkley Adam Benjamin

Classifications

• H10P72/0611

  Sorting devices · CPC title

• H10W72/5475

  multiple bond wires connected to common bond pads at both ends of the wires · CPC title

• H10W72/5473

  multiple bond wires connected to a common bond pad · CPC title

• H10W72/926

  Multiple bond pads having different sizes · CPC title

• H10W90/00

  Package configurations · CPC title