Semiconductor module arrangement

Patent metadata

Field	Value
Publication number	US-11538725-B2
Application number	US-202016937701-A
Country	US
Kind code	B2
Filing date	Jul 24, 2020
Priority date	Jul 26, 2019
Publication date	Dec 27, 2022
Grant date	Dec 27, 2022

Abstract

A semiconductor module arrangement includes a housing and at least one pair of semiconductor substrates arranged inside the housing. Each pair of semiconductor substrates includes first and second semiconductor substrates. The first semiconductor substrate includes a first dielectric insulation layer arranged between a first metallization layer and a third metallization layer, and a second dielectric insulation layer arranged between the third metallization layer and a second metallization layer. The second semiconductor substrate includes a first dielectric insulation layer arranged between a first metallization layer and a third metallization layer, and a second dielectric insulation layer arranged between the third metallization layer and a second metallization layer. The third metallization layer of the first semiconductor substrate is electrically coupled to a first electrical potential, and the third metallization layer of the second semiconductor substrate is electrically coupled to a second electrical potential that is opposite to the first electrical potential.

First claim

What is claimed is:

1. A semiconductor module arrangement, comprising:
a housing; and
at least one pair of semiconductor substrates arranged inside the housing, each pair of semiconductor substrates comprising a first semiconductor substrate and a second semiconductor substrate, wherein:
the first semiconductor substrate comprises a first dielectric insulation layer arranged between a first metallization layer and a third metallization layer, and a second dielectric insulation layer arranged between the third metallization layer and a second metallization layer;
the second semiconductor substrate comprises a first dielectric insulation layer arranged between a first metallization layer and a third metallization layer, and a second dielectric insulation layer arranged between the third metallization layer and a second metallization layer,
the third metallization layer of the first semiconductor substrate is electrically coupled to a first electrical potential; and
the third metallization layer of the second semiconductor substrate is electrically coupled to a second electrical potential having an opposite polarity as the first electrical potential such that a voltage is supplied via the third metallization layer of the first semiconductor substrate and the third metallization layer of the second semiconductor substrate.

2. The semiconductor module arrangement of claim 1 , wherein a DC voltage is supplied via the third metallization layer of the first semiconductor substrate and the third metallization layer of the second semiconductor substrate.

3. The semiconductor module arrangement of claim 1 , further comprising at least a first controllable semiconductor element and a second controllable semiconductor element.

4. The semiconductor module arrangement of claim 3 , wherein:
the first controllable semiconductor element is arranged on the first semiconductor substrate and comprises a control electrode and a load path formed between a first load electrode and a second load electrode; and
the second controllable semiconductor element is arranged on the second semiconductor substrate and comprises a control electrode and a load path formed between a first load electrode and a second load electrode.

5. The semiconductor module arrangement of claim 4 , wherein the load path of the first controllable semiconductor element and the load path of the second controllable semiconductor element are coupled in series.

6. The semiconductor module arrangement of claim 4 , wherein:
the first controllable semiconductor element is electrically coupled to the first metallization layer of the first semiconductor substrate by an electrically conductive connection layer;
the first controllable semiconductor element is further electrically coupled to the first metallization layer of the second semiconductor substrate by at least one electrical connection;
the first metallization layer of the second semiconductor substrate comprises at least a first section and a second section;
the second controllable semiconductor element is electrically coupled to the first section of the first metallization layer of the second semiconductor substrate by an electrically conductive connection layer; and
the second controllable semiconductor element is further electrically coupled to the second section of the first metallization layer of the second semiconductor substrate by at least one electrical connection.

7. The semiconductor module arrangement of claim 6 , wherein each electrical connection comprises one of a bonding wire, a bonding ribbon, a connection plate, and a conductor rail.

8. The semiconductor module arrangement of claim 3 , wherein:
the first metallization layer of the first semiconductor substrate comprises at least a first section, a second section, and a third section;
the first metallization layer of the second semiconductor substrate comprises at least a first section, a second section, and a third section;
one first controllable semiconductor element is arranged on the first section, and one second controllable semiconductor element is arranged on the second section of the first metallization layer of the first semiconductor substrate; and
another first controllable semiconductor element is arranged on the first section, and another second controllable semiconductor element is arranged on the second section of the first metallization layer of the second semiconductor substrate.

9. The semiconductor module arrangement of claim 8 , wherein:
the first section of the first metallization layer of the first semiconductor substrate is electrically coupled to the third metallization layer of the first semiconductor substrate by a via extending through the first dielectric insulation layer of the first semiconductor substrate; and
the third section of the first metallization layer of the second semiconductor substrate is electrically coupled to the third metallization layer of the second semiconductor substrate by a via extending through the first dielectric insulation layer of the second semiconductor substrate.

10. The semiconductor module arrangement of claim 8 , wherein:
the first metallization layer of the first semiconductor substrate further comprises a fourth section and a fifth section, the fourth section being electrically coupled to the third metallization layer of the first semiconductor substrate by a via extending through the first dielectric insulation layer of the first semiconductor substrate, and the fifth section being electrically coupled to the third metallization layer of the first semiconductor substrate by a via extending through the first dielectric insulation layer of the first semiconductor substrate; and
the first metallization layer of the second semiconductor substrate further comprises a fourth section and a fifth section, the fourth section being electrically coupled to the third metallization layer of the second semiconductor substrate by a via extending through the first dielectric insulation layer of the second semiconductor substrate, and the fifth section being electrically coupled to the third metallization layer of the second semiconductor substrate by a via extending through the first dielectric insulation layer of the second semiconductor substrate.

11. The semiconductor module arrangement of claim 10 , wherein:
the fourth section of the first metallization layer of the first semiconductor substrate is electrically coupled to the first section of the first metallization layer of the first semiconductor substrate; and
the fifth section of the first metallization layer of the second semiconductor substrate is electrically coupled to the third section of the first metallization layer of the second semiconductor substrate.

12. The semiconductor module arrangement of claim 10 , wherein:
the fifth section of the first metallization layer of the first semiconductor substrate is electrically coupled to the third section of the first metallization layer of the first semiconductor substrate; and
the fourth section of the first metallization layer of the second semiconductor substrate is electrically coupled to the first section of the first metallization layer of the second semiconductor substrate.

13. The semiconductor module arrangement of claim 8 , wherein:
the first controllable semiconductor element that is arranged on the first section of the first metallization layer of the first semiconductor substrate is further electrically coupled to the second section of the first metallization layer of the first semiconductor substrate by at least one electrical connection;
the second controllable semiconductor element that is ar

Assignees

• Infineon Technologies Ag

Inventors

• Domes Daniel

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H10W40/255

  having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates · CPC title