High voltage power module

US9839146B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9839146-B2
Application numberUS-201514918110-A
CountryUS
Kind codeB2
Filing dateOct 20, 2015
Priority dateOct 20, 2015
Publication dateDec 5, 2017
Grant dateDec 5, 2017

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A power module includes a number of sub-modules connected via removable jumpers. The removable jumpers allow the connections between one or more power semiconductor die in the sub-modules to be reconfigured, such that when the removable jumpers are provided, the power module has a first function and when the removable jumpers are removed, the power module has a second function. The removable jumpers may also allow for independent testing of the sub-modules. The power module may also include a multi-layer printed circuit board (PCB), which is used to connect one or more contacts of the power semiconductor die. The multi-layer PCB reduces stray inductance between the contacts and therefore improves the performance of the power module.

First claim

Opening claim text (preview).

What is claimed is: 1. A power module comprising: a power substrate; a first power semiconductor die on the power substrate and comprising a first contact and a second contact; a second power semiconductor die on the power substrate and comprising a first contact and a second contact; and a multi-layer printed circuit board (PCB) over the power substrate, the first power semiconductor die, and the second power semiconductor die and coupled between the first power semiconductor die and the second power semiconductor die such that: a first conductive layer of the multi-layer PCB is coupled between the first contact of the first power semiconductor die and the first contact of the second power semiconductor die; a second conductive layer of the multi-layer PCB is coupled between the second contact of the first power semiconductor die and the second contact of the second power semiconductor die; and the first conductive layer and the second conductive layer are separated by an insulating layer. 2. The power module of claim 1 wherein the power module is configured to block at least 3 kV. 3. The power module of claim 1 wherein the first power semiconductor die and the second power semiconductor die are metal-oxide semiconductor field-effect transistors (MOSFETs). 4. The power module of claim 3 wherein the first power semiconductor die and the second power semiconductor die comprise silicon carbide. 5. The power module of claim 3 wherein: the first contact of the first power semiconductor die and the first contact of the second power semiconductor die are gate contacts; and the second contact of the first power semiconductor die and the second contact of the second power semiconductor die are source contacts. 6. The power module of claim 1 further comprising: a first electrical connector coupled to the first conductive layer; and a second electrical connector coupled to the second conductive layer. 7. The power module of claim 6 wherein an inductance between the first electrical connector and the second electrical connector is less than about 15 nH. 8. The power module of claim 6 wherein the first electrical connector and the second electrical connector are provided in a micro-coaxial (MCX) connector. 9. The power module of claim 1 wherein the first power semiconductor die and the second power semiconductor die are part of a plurality of semiconductor die coupled in series between a third electrical connector and a fourth electrical connector. 10. The power module of claim 9 wherein the third electrical connector and the fourth electrical connector are bolted connectors with a width greater than about 30 mm. 11. The power module of claim 10 wherein an inductance between the third electrical connector and the fourth electrical connector is less than about 20 nH. 12. The power module of claim 1 wherein a width of the first conductive layer and the second conductive layer is greater than 10 mm. 13. The power module of claim 12 wherein the width of the first conductive layer and the second conductive layer is between 10 mm and 50 mm. 14. A power module comprising: a power substrate; a first power semiconductor die on the power substrate and comprising a first contact and a second contact; a second power semiconductor die on the power substrate and comprising a first contact and a second contact; and a printed circuit board (PCB) over the power substrate, the first power semiconductor die, and the second power semiconductor die and coupled between the first power semiconductor die and the second power semiconductor die such that: a first conductive layer of the PCB is coupled between the first contact of the first power semiconductor die and the first contact of the second power semiconductor die; a second conductive layer of the PCB is coupled between the second contact of the first power semiconductor die and the second contact of the second power semiconductor die; and the first conductive layer and the second conductive layer have a width greater than 10 mm. 15. The power module of claim 14 wherein the power module is configured to block at least 3 kV. 16. The power module of claim 14 wherein the first power semiconductor die and the second power semiconductor die are metal-oxide-semiconductor field-effect transistors (MOSFETs). 17. The power module of claim 16 wherein the first power semiconductor die and the second power semiconductor die comprise silicon carbide. 18. The power module of claim 16 wherein: the first contact of the first power semiconductor die and the first contact of the second power semiconductor die are gate contacts; and the second contact of the first power semiconductor die and the second contact of the second power semiconductor die are source contacts. 19. The power module of claim 14 further comprising: a first electrical connector coupled to the first conductive layer of the PCB; and a second electrical connector coupled to the second conductive layer of the PCB. 20. The power module of claim 19 wherein an inductance between the first electrical connector and the second electrical connector is less than 15 nH.

Assignees

Inventors

Classifications

  • multiple bond wires connected to common bond pads at both ends of the wires · CPC title

  • Snap-on arrangements, e.g. clips · CPC title

  • Package configurations · CPC title

  • Adaptable interconnections, e.g. fuses or antifuses · CPC title

  • H10W70/611Primary

    for connecting multiple chips together · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9839146B2 cover?
A power module includes a number of sub-modules connected via removable jumpers. The removable jumpers allow the connections between one or more power semiconductor die in the sub-modules to be reconfigured, such that when the removable jumpers are provided, the power module has a first function and when the removable jumpers are removed, the power module has a second function. The removable ju…
Who is the assignee on this patent?
Cree Inc
What technology area does this patent fall under?
Primary CPC classification H10W70/611. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 05 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).