Thin film transistors with spacer controlled gate length

Patent metadata

Field	Value
Publication number	US-11997847-B2
Application number	US-202217588938-A
Country	US
Kind code	B2
Filing date	Jan 31, 2022
Priority date	Mar 31, 2017
Publication date	May 28, 2024
Grant date	May 28, 2024

Abstract

Embodiments herein describe techniques for a semiconductor device including a TFT having a gate electrode with a gate length determined by a spacer. Embodiments may include a gate electrode above a substrate, a channel layer above the gate electrode, and a source electrode, a drain electrode, and a spacer above the channel layer. The drain electrode may be separated from the source electrode by the spacer. The drain electrode and the source electrode may have different widths or include different materials. Furthermore, the spacer may overlap with the gate electrode, hence the gate length of the gate electrode may be determined by the spacer width. Other embodiments may be described and/or claimed.

First claim

What is claimed is:

1. A method for forming a thin film transistor (TFT), the method comprising:
forming a gate electrode above a substrate;
forming a gate dielectric layer conformally covering the gate electrode and the substrate;
forming a channel layer above the gate dielectric layer;
forming a source electrode above the channel layer, wherein the source electrode is separated from another source electrode of an adjacent transistor by a pitch, and the source electrode has a first width;
subsequent to forming the source electrode, forming a spacer next to the source electrode and above the channel layer, wherein the spacer has a second width, and overlaps with the gate electrode; and
subsequent to forming the spacer, forming a drain electrode next to the spacer and above the channel layer, wherein the drain electrode has a third width, and wherein a sum of the first width, the second width, and the third width is less than the pitch.

2. The method of claim 1 , wherein the source electrode is a first source electrode, the spacer is a first spacer, and the method further comprising:
forming a second source electrode above the channel layer, wherein the second source electrode is separated from the first source electrode by the pitch; and
forming a second spacer between the drain electrode and the second source electrode and above the channel layer.

3. The method of claim 1 , wherein the second width is about 5% to 15% of the first width.

4. The method of claim 1 , wherein the source electrode includes a first conductive material, and the drain electrode includes a second conductive material different from the first conductive material.

5. The method of claim 1 , wherein the first width is different from the third width.

6. The method of claim 1 , further comprising:
forming a top dielectric layer above the source electrode, the drain electrode, and the spacer, wherein the spacer includes a first dielectric material, and the top dielectric layer includes a second dielectric material different from the first dielectric material.

7. The method of claim 1 , wherein the gate dielectric layer includes silicon and oxygen, silicon and nitrogen, yttrium and oxygen,
silicon, oxygen, and nitrogen, aluminum and oxygen, hafnium and oxygen, tantalum and oxygen, or titanium and oxygen.

8. The method of claim 1 , wherein the channel layer includes amorphous silicon, zinc (Zn), or oxygen (O).

9. The method of claim 1 , wherein the source electrode or the drain electrode includes gold (Au), platinum (Pt), ruthenium (Ru), iridium (Ir), titanium (Ti), aluminum (Al), copper (Cu), tantalum (Ta), tungsten (W), iridium-tantalum alloy (Ir—Ta), or indium-tin oxide (ITO).

10. The method of claim 1 , wherein a top surface of the spacer and a top surface of the source electrode are level with each other.

11. The method of claim 1 , wherein the second width of the spacer determines a gate length (Lg) of the gate electrode.

Assignees

• Intel Corp

Inventors

• Sharma Abhishek A
• Le Van H
• Dewey Gilbert
• Shivaraman Shriram
• Wang Yih
• Ghani Tahir
• Kavalieros Jack T

Classifications

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10D64/691

  comprising metallic compounds, e.g. metal oxides or metal silicates  (insulators comprising nitrogen H10D64/693) · CPC title

• H10D64/62

  Electrodes ohmically coupled to a semiconductor · CPC title

• H10D64/021

  using multiple gate spacer layers, e.g. bilayered sidewall spacers · CPC title

• H10D30/6756

  Amorphous oxide semiconductors · CPC title