Manufacturing method of thin film transistor and thin film transistor

Patent metadata

Field	Value
Publication number	US-2016013294-A1
Application number	US-201414425994-A
Country	US
Kind code	A1
Filing date	Jun 26, 2014
Priority date	Jan 28, 2014
Publication date	Jan 14, 2016
Grant date	—

Abstract

A manufacturing method of a thin film transistor and a thin film transistor are provided. In the manufacturing method, formation of pattern of a source electrode ( 7 ), a drain electrode ( 8 ) and an active layer ( 6 ) comprises: forming a semiconductor layer ( 10 ) and a conductive layer ( 11 ) that cover the whole substrate on the substrate in sequence; forming a first photoresist layer ( 4 ) at a region where the source electrode is to be formed and at a region where the drain electrode is to be formed on the conductive layer ( 11 ), respectively; forming a second photoresist layer ( 5 ) at least at a gap between the source electrode and the drain electrode that are to be formed on the conductive layer ( 11 ); conducting an etching process on the substrate with the first photoresist layer ( 4 ), the second photoresist layer ( 5 ), the semiconductor layer ( 10 ) and the conductive layer ( 11 ) formed thereon, so as to form pattern of the active layer ( 6 ), the source electrode ( 7 ) and the drain electrode ( 8 ).

First claim

1 . A manufacturing method of a thin film transistor, comprising: forming a gate electrode pattern and a gate insulating layer on a substrate, and forming patterns of a source electrode, a drain electrode and an active layer;
wherein forming patterns of the source electrode, the drain electrode and the active layer comprises: forming a semiconductor layer and a conductive layer that cover the whole substrate on the substrate in sequence; forming a first photoresist layer at a region where the source electrode is to be formed and at a region where the drain electrode is to be formed on the conductive layer, respectively; forming a second photoresist layer at least at a gap between the source electrode and the drain electrode that are to be formed on the conductive layer; and conducting an etching process on the substrate with the first photoresist layer, the second photoresist layer, the semiconductor layer and the conductive layer formed thereon, so as to form patterns of the active layer, the source electrode and the drain electrode.

2 . The method claimed as claim 1 , further comprising forming the second photoresist layer located on the first photoresist layer when the second photoresist layer is formed.

3 . The method claimed as claim 1 , wherein forming patterns of the active layer, the source electrode and the drain electrode further comprises:
conducting an etching process on the conductive layer, so as to retain the conductive layer in a region covered by the first photoresist layer and the second photoresist layer, and to expose the semiconductor layer in a region uncovered by the first photoresist layer and the second photoresist layer; conducting an etching process on the semiconductor layer, so as to remove the semiconductor layer in the region uncovered by the first photoresist layer and the second photoresist layer, with the semiconductor layer in a region covered by the first photoresist layer and the second photoresist layer serving as an active layer pattern; performing an ashing treatment on the second photoresist layer according to the thickness of the second photoresist, so as to expose the conductive layer in correspondence with a gap between the source electrode and the drain electrode that are to be formed; conducting an etching process on the conductive layer once again, so as to remove the conductive layer in correspondence with the gap between the source electrode and the drain electrode that are to be formed, and to form patterns of the source electrode and the drain electrode that are insulated from each other.

4 . The method claimed as claim 3 , after forming patterns of the active layer, the source electrode and the drain electrode, further comprising stripping off the first photoresist layer on the source electrode and the drain electrode.

5 . The method claimed as claim 1 , wherein the process of forming the gate electrode pattern and the gate insulating layer on the substrate comprises:
before patterns of the source electrode, the drain electrode and the active layer is formed, forming the gate electrode pattern on the substrate and the gate insulating layer located on the gate electrode pattern; or after patterns of the source electrode, the drain electrode and the active layer is formed, forming the gate insulating layer on the substrate and the gate electrode pattern located over the gate insulating layer.

6 . The method claimed as claim 1 , wherein a thickness of the first photoresist layer is in the range of 1.5 μm to 2.5 μm.

7 . The method claimed as claim 1 , wherein the second photoresist layer is a film layer with a uniform thickness; and a thickness of the second photoresist layer is in the range of 0.3 μm to 0.8 μm.

8 . The method claimed as claim 1 , wherein the distance between the source electrode and the drain electrode that are to be formed is in a range of 2.5 μm to 4.55 μm.

9 . The method claimed as claim 1 , wherein the active layer is made of amorphous silicon, polycrystalline silicon or a metal oxide semiconductor.

10 . A thin film transistor that is formed by using the method claimed as claim 1 .

11 . The method claimed as claim 3 , wherein the process of forming the gate electrode pattern and the gate insulating layer on the substrate comprises:
before patterns of the source electrode, the drain electrode and the active layer is formed, forming the gate electrode pattern on the substrate and the gate insulating layer located on the gate electrode pattern; or after patterns of the source electrode, the drain electrode and the active layer is formed, forming the gate insulating layer on the substrate and the gate electrode pattern located over the gate insulating layer.

12 . The method claimed as claim 3 , wherein a thickness of the first photoresist layer is in the range of 1.5 μm to 2.5 μm.

13 . The method claimed as claim 3 , wherein the second photoresist layer is a film layer with a uniform thickness; and a thickness of the second photoresist layer is in the range of 0.3 μm to 0.8 μm.

14 . The method claimed as claim 3 , wherein the distance between the source electrode and the drain electrode that are to be formed is in a range of 2.5 μm to 4.55 μm.

15 . The method claimed as claim 3 , wherein the active layer is made of amorphous silicon, polycrystalline silicon or a metal oxide semiconductor.

16 . The method claimed as claim 4 , wherein the process of forming the gate electrode pattern and the gate insulating layer on the substrate comprises:
before patterns of the source electrode, the drain electrode and the active layer is formed, forming the gate electrode pattern on the substrate and the gate insulating layer located on the gate electrode pattern; or after patterns of the source electrode, the drain electrode and the active layer is formed, forming the gate insulating layer on the substrate and the gate electrode pattern located over the gate insulating layer.

17 . The method claimed as claim 4 , wherein a thickness of the first photoresist layer is in the range of 1.5 μm to 2.5 μm.

18 . The method claimed as claim 4 , wherein the second photoresist layer is a film layer with a uniform thickness; and a thickness of the second photoresist layer is in the range of 0.3 μm to 0.8 μm.

19 . The method claimed as claim 4 , wherein the distance between the source electrode and the drain electrode that are to be formed is in a range of 2.5 μm to 4.55 μm.

20 . The method claimed as claim 4 , wherein the active layer is made of amorphous silicon, polycrystalline silicon or a metal oxide semiconductor.

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Optoelectronics

Inventors

• Hou Xuecheng
• Wu Tao
• Guo Jian

Classifications

• H10P50/693

  characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane · CPC title

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10D86/0231

  using masks, e.g. half-tone masks · CPC title