Thermal routing trench by additive processing

Patent metadata

Field	Value
Publication number	US-11996343-B2
Application number	US-202017114219-A
Country	US
Kind code	B2
Filing date	Dec 7, 2020
Priority date	Nov 26, 2016
Publication date	May 28, 2024
Grant date	May 28, 2024

Abstract

An integrated circuit has a substrate that includes a semiconductor material, and an interconnect region disposed on the substrate. The integrated circuit includes a thermal routing trench in the substrate. The thermal routing trench includes a cohered nanoparticle film in which adjacent nanoparticles are cohered to each other. The thermal routing trench has a thermal conductivity higher than the semiconductor material contacting the thermal routing trench. The cohered nanoparticle film is formed by an additive process.

First claim

What is claimed is:

1. A method of forming an integrated circuit, comprising:
forming a trench in a semiconductor substrate;
dispensing a first nanoparticle ink directly into the trench, in which the dispensing of the first nanoparticle ink follows a shape of the trench, and the first nanoparticle ink includes first nanoparticles and a first volatile material;
inducing cohesion of the first nanoparticles to form a first nanoparticle film in the trench;
dispensing a second nanoparticle ink directly into the trench and on the first nanoparticle film, in which the dispensing of the second nanoparticle ink follows the shape of the trench, and the second nanoparticle ink includes second nanoparticles and a second volatile material; and
inducing cohesion of the second nanoparticles to form a second nanoparticle film on the first nanoparticle film in the trench; and
forming an interconnect region over the trench.

2. The method of claim 1 , further comprising:
heating the dispensed first nanoparticle ink in the trench to remove the first volatile material; and
heating the dispensed second nanoparticle ink in the trench to remove the second volatile material.

3. The method of claim 2 , wherein heating the dispensed first nanoparticle ink in the trench includes heating the dispensed first nanoparticle ink in the trench at a temperature based on respective sizes of the first nanoparticles; and
wherein heating the dispensed second nanoparticle ink in the trench includes heating the dispensed second nanoparticle ink in the trench at a temperature based on respective sizes of the second nanoparticles.

4. The method of claim 1 , further comprising forming a liner of dielectric material in the trench before dispensing the first nanoparticle ink into the trench.

5. The method of claim 1 , wherein the first and second nanoparticles include at least one of: aluminum oxide, diamond, hexagonal boron nitride, cubic boron nitride, aluminum nitride, metal, graphene, graphene embedded in metal, graphite, graphitic carbon, or carbon nanotubes.

6. The method of claim 1 , wherein:
the first and second nanoparticles include at least one of: copper, nickel, palladium, platinum, iridium, rhodium, cerium, osmium, molybdenum, or gold.

7. The method of claim 1 , further comprising forming an oxide layer over the trench.

8. The method of claim 7 , further comprising forming first and second transistors in the semiconductor substrate, in which the first and second transistors are separated by the oxide layer.

9. The method of claim 8 , wherein forming first and second transistors in the semiconductor substrate comprises:
dispensing a sacrificial material on the first and second nanoparticle films in the trench;
forming first and second masks on a first region of the semiconductor substrate; and
performing an etch process to remove the sacrificial material and a second region of the semiconductor substrate exposed by the first and second masks; and
forming the oxide layer in the second region of the semiconductor substrate,
wherein forming the first and second transistors in the semiconductor substrate includes forming the first and second transistors in the first region of the semiconductor substrate.

10. The method of claim 1 , wherein the trench is a first trench, and the method further comprises:
forming the first and second trenches in the semiconductor substrate; and
filling the second trench with an oxide material.

11. The method of claim 10 , wherein the first and second trenches have a same depth from a surface of the semiconductor substrate.

12. The method of claim 1 , further comprising forming a dielectric layer over the semiconductor substrate,
wherein the trench is formed in the dielectric layer and in the semiconductor substrate; and
wherein the interconnect region is formed in the dielectric layer.

13. The method of claim 1 , wherein inducing cohesion of the first and second nanoparticles includes a scanned laser heating process, a flash heating process, or a spike heating process.

14. The method of claim 1 , further comprising forming a layer of graphitic material on the second nanoparticle film.

15. The method of claim 14 , wherein forming the layer of graphitic material on the second nanoparticle film includes flowing a reagent gas over the second nanoparticle film.

16. The method of claim 15 , wherein the reagent gas includes at least one of: methane, straight chain alkanes, alcohols, or cyclic hydrocarbons.

17. The method of claim 1 , wherein dispensing the first nanoparticle ink directly into the trench includes moving a dispensing apparatus of the first nanoparticle ink laterally with respect to the semiconductor substrate.

18. The method of claim 1 , wherein the cohesion of the first and second nanoparticles is based on at least one of: a physical mechanism involving diffusion of atoms between adjacent first and second nanoparticles, or a chemical mechanism involving reaction of atoms between adjacent first and second nanoparticles.

19. The method of claim 1 , wherein the dispensing of the first nanoparticle ink is by a first additive process, and wherein the dispensing of the second nanoparticle ink is by a second additive process, and each of the first and second additive processes includes a respective discrete droplet dispensing process, a respective continuous extrusion process, a respective direct laser transfer process, a respective electrostatic deposition process, or a respective electrochemical deposition process.

20. The method of claim 1 , wherein the first and second volatile materials are a same material.

21. A method of forming an integrated circuit, comprising:
forming a trench in a semiconductor substrate;
dispensing a nanoparticle ink directly into the trench, in which the dispensing of the nanoparticle ink follows a shape of the trench, and the nanoparticle ink includes nanoparticles and a volatile material;
inducing cohesion of the nanoparticles to form a nanoparticle film in the trench; and
forming a layer of graphitic material on the nanoparticle film by flowing a reagent gas over the nanoparticle film.

22. The method of claim 21 , wherein the reagent gas includes at least one of: methane, straight chain alkanes, alcohols, or cyclic hydrocarbons.

Assignees

• Texas Instruments Inc

Inventors

• Cook Benjamin Stassen
• Venugopal Archana
• Colombo Luigi
• Doering Robert Reid

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P14/416

  of highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers · CPC title

• H10P14/412

  Deposition of metallic or metal-silicide materials · CPC title

• H10W72/536

  the connected ends being ball-shaped · CPC title

• H10W40/228

  the projecting parts being wire-shaped or pin-shaped · CPC title