Memory arrays and methods used in forming a memory array comprising strings of memory cells

Patent metadata

Field	Value
Publication number	US-11996151-B2
Application number	US-202117315727-A
Country	US
Kind code	B2
Filing date	May 10, 2021
Priority date	May 10, 2021
Publication date	May 28, 2024
Grant date	May 28, 2024

Abstract

A memory array comprising laterally-spaced memory blocks individually comprises a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. The laterally-spaced memory blocks in a lower one of the conductive tiers comprises elemental-form metal that extends longitudinally-along the laterally-spaced memory blocks proximate laterally-outer sides of the laterally-spaced memory blocks. A metal silicide or a metal-germanium compound is directly against laterally-inner sides of the elemental-form metal in the lower conductive tier and that extends longitudinally-along the laterally-spaced memory blocks in the lower conductive tier. The metal of the metal silicide or of the metal-germanium compound is the same as that of the elemental-form metal. Other embodiments, including method, are disclosed.

First claim

The invention claimed is:

1. A method used in forming a memory array comprising strings of memory cells, comprising:
forming a conductor tier comprising conductor material on a substrate;
forming a lower portion of a stack that will comprise vertically-alternating first tiers and second tiers above the conductor tier, the stack comprising laterally-spaced memory-block regions, material of the first tiers being of different composition from material of the second tiers, the lower portion comprising:
a lowest of the first tiers comprising sacrificial material;
an uppermost tier; and
an intermediate tier vertically between the lowest first tier and the uppermost tier, the intermediate tier comprising at least one of silicon and germanium;

forming lower horizontally-elongated trenches through the uppermost tier and into the intermediate tier in the lower portion, the lower horizontally-elongated trenches individually being between immediately-laterally-adjacent of the memory-block regions;
reacting a metal halide with the at least one of the silicon and germanium to form sidewalls of the lower horizontally-elongated trenches in the intermediate tier to comprise the metal of the metal halide and that extends longitudinally-along the laterally-spaced memory-block regions in the intermediate tier;
forming the vertically-alternating first tiers and second tiers of an upper portion of the stack above the lower portion, forming channel-material strings that extend through the first tiers and the second tiers in the upper portion to the lowest first tier in the lower portion, and forming upper horizontally-elongated trenches in the upper portion that are individually directly above and extend longitudinally-along individual of the lower horizontally-elongated trenches; and
through the upper and lower horizontally-elongated trenches, replacing the sacrificial material in the lowest first tier with conductive material that directly electrically couples together channel material of the channel-material strings and the conductor material of the conductor tier.

2. The method of claim 1 wherein the reacting forms the metal of the metal halide to extend longitudinally-along the immediately-laterally-adjacent memory-block regions in the intermediate tier within the immediately-laterally-adjacent memory block regions.

3. The method of claim 2 wherein the reacting forms the metal of the metal halide to extend laterally into the immediately-laterally-adjacent memory block regions to be everywhere laterally-spaced from locations of the channel-material strings.

4. The method of claim 1 wherein the intermediate tier comprises silicon in elemental form.

5. The method of claim 1 wherein the intermediate tier comprises germanium in elemental form.

6. The method of claim 1 wherein the intermediate tier comprises silicon and germanium.

7. The method of claim 6 wherein the silicon and germanium together are in alloy form.

8. The method of claim 1 wherein the metal of the sidewalls of the lower horizontally-elongated trenches in the intermediate tier is in elemental form.

9. The method of claim 8 comprising forming a metal silicide or a metal-germanium compound that is directly against laterally-inner sides of the elemental-form metal and that extends longitudinally-along the laterally-spaced memory blocks in the intermediate tier.

10. The method of claim 9 comprising forming the metal silicide.

11. The method of claim 9 comprising forming the metal-germanium compound.

12. The method of claim 9 comprising forming both of the metal silicide and the metal-germanium compound.

13. The method of claim 1 wherein the intermediate tier is of different composition from that of the uppermost tier.

14. The method of claim 1 wherein the lower portion comprises an intervening tier of different composition from that of the intermediate tier vertically between the intermediate tier and the lowest first tier.

15. The method of claim 1 wherein the lower horizontally-elongated trenches as initially formed extend through the intermediate tier, but not to the lowest first tier.

16. The method of claim 15 wherein,
the forming lower horizontally-elongated trenches comprises etching;
the lower portion comprises an intervening tier of different composition from that of the intermediate tier vertically between the intermediate tier and the lowest first tier; and
the etching stopping on the intervening tier.

17. The method of claim 1 wherein the lower portion comprises a lowest of the second tiers that is below the lowest first tier.

18. The method of claim 17 comprising removing the lowest second tier before the replacing.

19. A method used in forming a memory array comprising strings of memory cells, comprising:
forming a conductor tier comprising conductor material on a substrate;
forming a lower portion of a stack that will comprise vertically-alternating first tiers and second tiers above the conductor tier, the stack comprising laterally-spaced memory-block regions, material of the first tiers being of different composition from material of the second tiers, the lower portion comprising:
a lowest of the first tiers comprising sacrificial material;
an uppermost tier; and
an intermediate tier vertically between the lowest first tier and the uppermost tier, the intermediate tier comprising at least one of silicon and germanium;

forming lower horizontally-elongated trenches through the uppermost tier and into the intermediate tier in the lower portion, the lower horizontally-elongated trenches individually being between immediately-laterally-adjacent of the memory-block regions;
reacting a metal halide with the at least one of the silicon and germanium to form sidewalls of the lower horizontally-elongated trenches in the intermediate tier to comprise elemental-form metal that is the same metal as that of the metal halide and that extends longitudinally-along the laterally-spaced memory-block regions in the intermediate tier;
after the reacting, forming sacrificial lines comprising the elemental-form metal in the lower horizontally-elongated trenches;
forming the vertically-alternating first tiers and second tiers of an upper portion of the stack above the lower portion;
forming channel-material strings that extend through the first tiers and the second tiers in the upper portion to the lowest first tier in the lower portion;
forming upper horizontally-elongated trenches in the upper portion that are individually directly above, extend longitudinally-along, and extend to individual of the sacrificial lines in the lower portion;
through the upper horizontally-elongated trenches, removing the elemental-form metal of the sacrificial lines that is in the lower portion; and
after the removing and through the upper and lower horizontally-elongated trenches, replacing the sacrificial material in the lowest first tier with conductive material that directly electrically couples together channel material of the channel-material strings and the conductor material of the conductor tier.

20. The method of claim 19 wherein the individual sacrificial lines comprise an exterior lining as line sidewalls and as a line base, the exterior lining being of different composition from the elemental-form metal, the elemental-form metal being laterally-between and directly above the line sidewalls and the line base, respectively.

21. The method of claim 19 wherein the reacting forms the elemental-form metal of the metal halide to e

Assignees

• Micron Technology Inc

Inventors

• Greenlee Jordan D
• Hopkins John D
• Li Andrew
• Scarbrough Alyssa N

Classifications

• H10D62/832

  being Group IV materials comprising two or more elements, e.g. SiGe · CPC title

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• H01L29/161

  Electricity · mapped topic

• H10B41/10

  characterised by the top-view layout · CPC title

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title