Power management and staggering transitioning from idle mode to operational mode

Patent metadata

Field	Value
Publication number	US-11994925-B2
Application number	US-202016947446-A
Country	US
Kind code	B2
Filing date	Jul 31, 2020
Priority date	Apr 10, 2020
Publication date	May 28, 2024
Grant date	May 28, 2024

Abstract

A system includes a first and a second group of cores in a multicore system. Each core of the first/second group is configured to process data. Each core within the first/second group is configured to enter into an idle state in response to being idle for a first/second period of time respectively. Every idle core in the first/second group is configured to transition out of the idle state and into an operational mode in response to receiving a signal having a first/second value respectively and further in response to having a pending operation to process.

First claim

What is claimed is:

1. A system comprising:
a first plurality of cores within a multicore system, wherein the first plurality of cores is associated with a first group; and
a second plurality of cores within the multicore system, wherein the second plurality of cores is associated with a second group, wherein the first and the second plurality of cores are configured to process data,
wherein each core of the first and the second plurality of cores receives a clocking signal, and wherein the first group is associated with a first number based on a first number of clock pulses of the clocking signal and wherein the second group is associated with a second number based on a second number of clock pulses of the clocking signal,
wherein a wake signal is generated for an idle core of the first group to move the idle core of the first group from an idle mode to an operational mode responsive to the clocking signal reaching the first number of clock pulses, and wherein a wake signal is generated for an idle core of the second group to move the idle core of the second group from the idle mode to the operational mode responsive to the clocking signal reaching the second number of clock pulses, wherein the idle core of the first group and the idle core of the second group reach the operational mode in a staggered fashion to limit a sudden power surge and wherein the idle core of the first group becomes active and capable of processing data in the operational mode and wherein the idle core of the second group becomes active and capable of processing data in the operational mode, and wherein two idle cores within the first plurality of cores transition out of the idle mode into the operational mode if the first number of clock pulses is reached and further if the two idle cores have a pending operation to process.

2. The system of claim 1 , wherein the wake signal for the idle core of the first group is generated responsive to the clocking signal reaching the first number of clock pulses and if the idle core of the first group has an operation to process.

3. The system of claim 1 , wherein moving the idle core of the first group to the operational mode and moving the idle core of the second group to the operational mode occurs staggered in time and based on a number of clock pulses of the clocking signal.

4. The system of claim 1 , wherein each core of the first group and the second group comprises a counter configured to count a number of the clock pulses of the clocking signal, and wherein the wake signal for the idle core of the first group is generated when the count of the clock pulses reaches the first number of clock pulses, and wherein the wake signal for the idle core of the second group is generated when the count of the clock pulses of the clocking signal reaches the second number of clock pulses.

5. The system of claim 1 , wherein a wake signal is generated for more than one idle core in the first group responsive to the clock pulses of the clocking signal reaching the first number of clock pulses.

6. The system of claim 5 , wherein a wake signal is generated for more than one idle core in the second group responsive to the clock pulses of the clocking signal reaching the second number of clock pulses.

7. The system of claim 6 , wherein the wake signal for the more than one idle core in the first group is generated at a different time than from the wake signal for the more than one idle core in the second group.

8. The system of claim 1 , wherein the first number of clock pulses and the second number of clock pulses are user programmable.

9. The system of claim 1 , wherein each core of the first group comprises a timer configured to track a duration that the each core of the first group is idle, and wherein the each core in the first group that is idle for a first predetermined amount of time enters into an idle state based on the clocking signal.

10. The system of claim 9 , wherein each core of the second group comprises a timer configured to track a duration that the each core of the second group is idle, and wherein the each core in the second group that is idle for a second predetermined amount of time enters into an idle state based on the clocking signal.

11. The system of claim 10 , wherein the first predetermined amount of time is different from the second predetermined amount of time.

12. The system of claim 10 , wherein the first predetermined amount of time and the second predetermined amount of time are user programmable.

13. A system comprising:
a first core within a multicore system, wherein the first core receives a clocking signal and a timer tick signal, wherein the first core includes:
a first timer configured to track an amount of time that the first core is idle and wherein the first timer generates an idle signal to cause the first core to enter into an idle mode responsive to the amount of time reaching a first threshold of time;
a first counter configured increment in response to each tick of the timer tick signal, wherein a trigger signal is generated to cause the first core to transition out of the idle mode if the first core is in idle mode and if a value of the first counter reaches a first stagger value; and

a second core within the multicore system, wherein the second core receives the clocking signal and the timer tick signal, wherein the first core and the second core are configured to process data,
wherein the second core includes:
a second timer configured to track an amount of time that the second core is idle and wherein the second timer generates an idle signal to cause the second core to enter into an idle mode responsive to the amount of time reaching a second threshold of time;
a second counter configured increment in response to each tick of the timer tick signal, wherein a trigger signal is generated to cause the second core to transition out of the idle mode if the second core is in idle mode and if a value of the second counter reaches a second stagger value, wherein the first core and the second core transition out of the idle mode in a staggered fashion to limit a sudden power surge if the first core and the second are within different groups within the multicore system, and wherein the first core and the second core transition out of the idle mode simultaneously if the first core and the second core are within a same group within the multicore system and further if the second counter reaches the second stagger value at a same time that the first counter reaches the first stagger value.

14. The system of claim 13 , wherein each tick for the timer tick signal is associated with a number of clock pulses of the clocking signal.

15. The system of claim 13 , wherein the first threshold of time is different from the second threshold of time.

16. The system of claim 15 , wherein the first threshold of time and the second threshold of time are user programmable.

17. The system of claim 13 , wherein the first stagger value is different from the second stagger value.

18. The system of claim 17 , wherein the first stagger value and the second stagger value are user programmable.

19. The system of claim 13 , wherein the first core and the second core are prevented from transitioning from an idle mode to an operational mode at a same time.

20. The system of claim 13 , wherein the trigger signal is generated to cause the first core to transition out of the idle mode if the first core is in idle mode and if the value of the first counter reaches the first stagger value and further if the fi

Assignees

• Marvell Asia Pte Ltd

Inventors

• Sripada Srinivas
• Chen Chia-Hsin
• Sodani Avinash
• Bhattarai Atul
• Jayakumar Nikhil

Classifications

• G06F1/3203 Primary

  Power management, i.e. event-based initiation of a power-saving mode · CPC title

• G06F1/08

  Clock generators with changeable or programmable clock frequency · CPC title

• G06F1/10

  Distribution of clock signals {, e.g. skew} · CPC title

• G06F1/324 Primary

  by lowering clock frequency · CPC title

• G06F1/3228 Primary

  Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands · CPC title