Dynamic power management optimization

Patent metadata

Field	Value
Publication number	US-2016378168-A1
Application number	US-201514751515-A
Country	US
Kind code	A1
Filing date	Jun 26, 2015
Priority date	Jun 26, 2015
Publication date	Dec 29, 2016
Grant date	—

Abstract

Systems, apparatuses, and methods for managing power usage of integrated circuits. One or more processor cores may be powered down when the system is idle. Even if there is no user activity, the processor core(s) may be woken up periodically for background downloads to retrieve the latest status for social media and other applications. Additionally, a power management unit may track the average number of active cores and the average core utilization. If the average number of active cores is less than a first threshold and the average core utilization is less than a second threshold, the power management unit may generate a request to offline one or more cores. Still further, when the processor's skin temperature is above a threshold and all of the cores are operating at the lowest acceptable operating point, one or more cores may be powered down.

First claim

What is claimed is:

1 . A method comprising:
initiating power down of a compute unit; determining a value of a wakeup timer based at least in part on a history of activity of the compute unit; starting the wakeup timer; and powering down the compute unit until the wakeup timer expires.

2 . The method as recited in claim 1 , further comprising:
setting the wakeup timer to a first value responsive to determining an activity indicator is less than a first threshold; and setting the wakeup timer to a second value responsive to determining the activity indicator is greater than the first threshold, wherein the second value is less than the first value.

3 . The method as recited in claim 2 , wherein the activity indicator is a counter and the method further comprises incrementing the counter responsive to detecting a memory access by the compute unit during a given interval.

4 . The method as recited in claim 3 , further comprising decrementing the counter responsive to detecting no memory accesses by the compute unit during the given interval.

5 . The method as recited in claim 1 , wherein the compute unit is a first core of a multi-core processor, and wherein the method further comprises:
calculating an average number of active cores for the multi-core processor; calculating an average core utilization of the multi-core processor; and generating a request to power down the first core responsive to determining the average number of active cores is less than a first threshold and the average core utilization is less than a second threshold.

6 . The method as recited in claim 5 , further comprising powering up a second core responsive to determining the average core utilization is above a third threshold.

7 . The method as recited in claim 1 , wherein the compute unit is a first core of a multi-core processor, and wherein the method further comprises:
monitoring a temperature of the multi-core processor; generating a request to power down the first core responsive to determining the temperature is above a threshold and all cores of the multi-core are operating at a lowest acceptable operating point.

8 . A system comprising:
a memory; a compute unit coupled to the memory; a power management unit coupled to the compute unit, wherein the power management unit is configured to:
determine a value of a wakeup timer based at least in part on a history of activity of the compute unit;
start the wakeup timer; and
power down the compute unit until the wakeup timer expires.

9 . The system as recited in claim 8 , wherein the power management unit is further configured to:
set the wakeup timer to a first value responsive to determining an activity indicator is less than a first threshold; and set the wakeup timer to a second value responsive to determining the activity indicator is greater than the first threshold, wherein the second value is less than the first value.

10 . The system as recited in claim 9 , wherein the activity indicator is a counter and the power management unit is further configured to increment the counter responsive to detecting a memory or input/output (I/O) access by the compute unit during a given interval.

11 . The system as recited in claim 10 , wherein the power management unit is further configured to decrement the counter responsive to detecting no memory or I/O accesses by the compute unit during the given interval.

12 . The system as recited in claim 8 , wherein the compute unit is a first core of a multi-core processor, and wherein the power management unit is configured to:
calculate an average number of active cores for the multi-core processor; calculate an average core utilization of the multi-core processor; and generate a request to power down the first core responsive to determining the average number of active cores is less than a first threshold and the average core utilization is less than a second threshold.

13 . The system as recited in claim 12 , wherein the power management unit is further configured to power up a second core responsive to determining the average core utilization is above a third threshold.

14 . The system as recited in claim 8 , wherein the compute unit is a first core of a multi-core processor, and wherein the power management unit is configured to:
monitor a temperature of the multi-core processor; and generate a request to power down the first core responsive to determining the temperature is above a threshold and all cores of the multi-core are operating at a lowest acceptable operating point.

15 . A non-transitory computer readable storage medium storing program instructions, wherein the program instructions are executable by a processor to:
initiate power down of a compute unit; determine a value of a wakeup timer based at least in part on a history of activity of the compute unit; start the wakeup timer; and power down the compute unit until the wakeup timer expires.

16 . The non-transitory computer readable storage medium as recited in claim 15 , wherein the program instructions are further executable by a processor to:
set a wakeup timer to a first value responsive to determining an activity indicator is less than a first threshold; and set the wakeup timer to a second value responsive to determining the activity indicator is greater than the first threshold, wherein the second value is less than the first value.

17 . The non-transitory computer readable storage medium as recited in claim 16 , wherein the activity indicator is a counter, wherein the program instructions are further executable by a processor to increment the counter responsive to detecting a memory access by the compute unit during a given interval.

18 . The non-transitory computer readable storage medium as recited in claim 17 , wherein the program instructions are further executable by a processor to decrementing the counter responsive to detecting no memory accesses by the compute unit during the given interval.

19 . The non-transitory computer readable storage medium as recited in claim 15 , wherein the compute unit is a first core of a multi-core processor, wherein prior to initiating power down of the first core, the program instructions are executable by a processor to:
calculate an average number of active cores for the multi-core processor; calculate an average core utilization of the multi-core processor; and generate a request to power down the first core responsive to determining the average number of active cores is less than a first threshold and the average core utilization is less than a second threshold.

20 . The non-transitory computer readable storage medium as recited in claim 19 , wherein the program instructions are further executable by a processor to power up a second core responsive to determining the average core utilization is above a third threshold.

Assignees

• Advanced Micro Devices Inc

Inventors

• Branover Alexander J
• Jain Ashish
• Gada Sridhar V

Classifications

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• G06F1/3287 Primary

  by switching off individual functional units in the computer system · CPC title

• G06F1/3237

  by disabling clock generation or distribution · CPC title

• G06F1/3203

  Power management, i.e. event-based initiation of a power-saving mode · CPC title

• G06F1/3243

  Power saving in microcontroller unit · CPC title