Fabrication of gate-all-around integrated circuit structures having pre-spacer deposition cut gates

Patent metadata

Field	Value
Publication number	US-11990472-B2
Application number	US-202017030212-A
Country	US
Kind code	B2
Filing date	Sep 23, 2020
Priority date	Sep 23, 2020
Publication date	May 21, 2024
Grant date	May 21, 2024

Abstract

Gate-all-around integrated circuit structures having pre-spacer-deposition cut gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. The integrated circuit structure also includes a dielectric structure having a first portion forming a gate spacer along sidewalls of the first gate stack, a second portion forming a gate spacer along sidewalls of the second gate stack, and a third portion completely filling the gap, the third portion continuous with the first and second portions.

First claim

What is claimed is:

1. An integrated circuit structure, comprising:
a first vertical arrangement of horizontal nanowires;
a second vertical arrangement of horizontal nanowires;
a first gate stack over the first vertical arrangement of horizontal nanowires;
a second gate stack over the second vertical arrangement of horizontal nanowires, an end of the second gate stack spaced apart from an end of the first gate stack by a gap; and
a dielectric structure comprising a first portion forming a gate spacer along sidewalls of the first gate stack, a second portion forming a gate spacer along sidewalls of the second gate stack, and a third portion completely filling the gap, the third portion continuous with the first and second portions.

2. The integrated circuit structure of claim 1 , further comprising:
a first pair of epitaxial source or drain structures at first and second ends of the first vertical arrangement of horizontal nanowires; and
a second pair of epitaxial source or drain structures at first and second ends of the second vertical arrangement of horizontal nanowires.

3. The integrated circuit structure of claim 2 , further comprising:
a first pair of conductive contacts on the first pair of epitaxial source or drain structures; and
a second pair of conductive contacts on the second pair of epitaxial source or drain structures.

4. The integrated circuit structure of claim 2 , wherein the first and second pairs of epitaxial source or drain structures are first and second pairs of non-discrete epitaxial source or drain structures.

5. The integrated circuit structure of claim 2 , wherein the first and second pairs of epitaxial source or drain structures are first and second pairs of discrete epitaxial source or drain structures.

6. An integrated circuit structure, comprising:
a first vertical arrangement of horizontal nanowires;
a second vertical arrangement of horizontal nanowires;
a gate stack over the first vertical arrangement of horizontal nanowires;
a gate plug over the second vertical arrangement of horizontal nanowires, an end of the gate plug spaced apart from an end of the gate stack by a gap; and
a dielectric structure comprising a first portion forming a gate spacer along sidewalls of the gate stack, a second portion forming a spacer along sidewalls of the gate plug, and a third portion completely filling the gap, the third portion continuous with the first and second portions.

7. The integrated circuit structure of claim 6 , further comprising a seam between the third portion of the dielectric structure and the gate plug.

8. The integrated circuit structure of claim 6 , further comprising:
a first pair of epitaxial source or drain structures at first and second ends of the first vertical arrangement of horizontal nanowires; and
a second pair of epitaxial source or drain structures at first and second ends of the second vertical arrangement of horizontal nanowires.

9. The integrated circuit structure of claim 8 , further comprising:
a first pair of conductive contacts on the first pair of epitaxial source or drain structures; and
a second pair of conductive contacts on the second pair of epitaxial source or drain structures.

10. The integrated circuit structure of claim 8 , wherein the first and second pairs of epitaxial source or drain structures are first and second pairs of non-discrete epitaxial source or drain structures.

11. The integrated circuit structure of claim 8 , wherein the first and second pairs of epitaxial source or drain structures are first and second pairs of discrete epitaxial source or drain structures.

Assignees

• Intel Corp

Inventors

• Guler Leonard P
• Harper Michael K
• Hsu William
• Guha Biswajeet
• Ghani Tahir
• Zussblatt Niels
• Tan Jeffrey Miles
• Kriegel Benjamin
• Haran Mohit K
• Patel Reken
• Golonzka Oleg
• Hasan Mohammad

Classifications

• H10D88/00

  Three-dimensional [3D] integrated devices · CPC title

• H10D62/119

  Nanowire, nanosheet or nanotube semiconductor bodies · CPC title

• H10D30/6219

  characterised by the source or drain electrodes · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title