Storage system

Patent metadata

Field	Value
Publication number	US-11990201-B2
Application number	US-202217657942-A
Country	US
Kind code	B2
Filing date	Apr 4, 2022
Priority date	Jan 14, 2021
Publication date	May 21, 2024
Grant date	May 21, 2024

Abstract

A storage system includes: a memory, configured to write or read a plurality of pieces of data during a read-write operation, the plurality of pieces of data being divided into M bytes, and each byte having N pieces of data; and an encoding circuit, configured to in the encoding stage, generate X first check codes based on the two or more pieces of data in each byte, generate Y second check codes based on all data of two or more bytes of the M bytes in the encoding stage, and generate a third check code based on the plurality of pieces of data, the X first check codes and the Y second check codes. The first check codes, the second check codes and the third check code are used to determine an error state of the plurality of pieces of data.

First claim

What is claimed is:

1. A storage system, comprising:
a memory, configured to write or read a plurality of data bits during a read-write operation, the plurality of data bits being divided into M bytes, and each byte having N data bits; and
an encoding circuit, configured to:
generate X first check codes based on two or more data bits of the plurality of data bits in each byte in an encoding stage, bit locations of the two or more data bits corresponding to a same first check code being identical in different bytes;
generate Y second check codes based on all data of two or more bytes of the M bytes in the encoding stage; and
generate a third check code based on the plurality of data bits, the X first check codes and the Y second check codes;
wherein the X first check codes, the Y second check codes and the third check code are used to determine an error state of the plurality of data bits; and
wherein when the plurality of data bits have a 1-bit error, the Y second check codes are used to locate a specific byte having the 1-bit error, and
the X first check codes are used to locate a specific bit having the 1-bit error; and
wherein M, N, X, and Y are all positive natural numbers.

2. The storage system of claim 1 , wherein the encoding circuit comprises: a first encoding circuit configured to generate the X first check codes, the X first check codes constitutes X bits of first binary numbers; and
wherein 2 x ≥N,
each first check code is obtained by executing a first encoding operation on the one or more data bits in respective bytes, and
a bit location combination in the byte corresponding to the two or more data bits corresponding to any first check code is different from a bit location combination corresponding to the two or more data bits corresponding to other first check code.

3. The storage system of claim 2 , wherein the N data bits are located in 0th to (N−1)th bits incremented in accordance with natural numbers, and
a first check code set obtained by selecting any bit for the first encoding operation is different from a first check code set obtained by selecting other bit for the first encoding operation.

4. The storage system of claim 2 , wherein N is 8, X is 3, and
the first encoding operation comprising XOR or XNOR; and
the first encoding circuit is configured such that in X bits of first binary numbers, the first check code at a lowest bit is XOR or XNOR of data in a 1st, 3rd, 5th and 7th bits in all the bytes, the first check code at a highest bit is XOR or XNOR of data of a 4th, 5th, 6th and 7th bits in all the bytes, and the first check code at a middle bit is XOR or XNOR of data of a 2nd, 3rd, 6th and 7th bits in all the bytes.

5. The storage system of claim 2 , wherein the encoding circuit further comprises: a second encoding circuit configured to generate Y second check codes, the Y second check codes constitutes Y bits of second binary numbers;
wherein 2 Y ≥M, each second check code is obtained by executing a second encoding operation on two or more bytes of the M bytes.

6. The storage system of claim 5 , wherein the second encoding operation comprises XNOR or XOR; wherein the second encoding circuit comprises:
a first-level operation circuit, configured to execute XOR or XNOR on all data of two selected bytes and store two or more first operation results, each first operation result being an XOR result or an XNOR result of the two selected bytes; and
a second-level operation circuit, configured to execute XOR or XNOR on at least two of the first operation results, generate second check codes, and generate Y second check codes based on different encoding requirements.

7. The storage system of claim 6 , wherein the first-level operation circuit comprises: a first operation sub-circuit, configured to execute XOR or XNOR on all data of a same byte and store second operation results; and
a second operation sub-circuit, configured to execute XOR or XNOR on two of the second operation results and obtain a first operation result.

8. The storage system of claim 5 , wherein the second encoding circuit is configured such that a number of times that each byte participates in the second encoding operation is α,
α satisfies: (Y−1)/2α(Y+1)/2, and
α is an integer greater than or equal to 0.

9. The storage system of claim 8 , wherein M is 16, Y is 5; wherein the M bytes are divided into 0th to 15th bytes incremented in accordance with natural numbers, the Y second check codes being divided into 3rd to 7th second check codes incremented in accordance with natural numbers;
wherein the 3rd second check code is XOR or XNOR of all data of 0th, 2nd, 3rd, 4th, 5th, 6th, and 8th bytes,
the 4th second check code is XOR or XNOR of all data of 0th, 1st, 4th, 5th, 7th, 9th, 10th, and 12th bytes,
the 5th second check code is XOR or XNOR of all data of 1st, 2nd, 4th, 6th, 9th, 11th, 13th, and 14th bytes,
the 6th second check code is XOR or XNOR of all data of 3rd, 5th, 6th, 7th, 10th, 11th, 14th, and 15th bytes, and
the 7th second check code is XOR or XNOR of all data of 8th, 9th, 10th, 11th, 12th, 13th, and 15th bytes.

10. The storage system of claim 5 , wherein the encoding circuit further comprises:
a third encoding circuit connected with an output end of the first encoding circuit and an output end of the second encoding circuit, and configured to receive the plurality of data bits and generate the third check code, and
the third check code is obtained by executing a fifth encoding operation on the plurality of data bits, the X first check codes and the Y second check codes.

11. The storage system of claim 2 , wherein the encoding circuit comprises: a comparison circuit, configured to execute the XOR or XNOR on all data of any two bytes or execute XOR or XNOR on the two or more data bits.

12. The storage system of claim 11 , wherein the comparison circuit comprises:
a first common circuit, connected to a power signal and controlling outputting of the power signal based on a first signal and a second signal, the first signal being inverted with respect to the second signal;
a second common circuit, connected to a grounding signal and controlling outputting of the grounding signal based on the first signal and the second signal;
a first logic circuit, connected between the first common circuit and the second common circuit, configured to receive a third signal and a fourth signal, the third signal being inverted with respect to the fourth signal, and configured to output a first operation signal, the first operation signal being XOR of the first signal and the third signal; and
a second logic circuit, connected between the first common circuit and the second common circuit, configured to receive the third signal and the fourth signal and output a second operation signal, the second operation signal being XNOR of the first signal and the third signal.

13. The storage system of claim 12 , wherein the first common circuit comprises:
a zeroth PMOS transistor, having a gate for receiving the first signal and a source connected to the power signal; and
a seventh PMOS transistor, having a gate for receiving the second signal and a source connected to the power signal;
and wherein the second common circuit comprises:
a zeroth NMOS transistor, having a gate for receiving the first signal and a source connected to the grounding signal; and
a seventh NMOS transistor, having a gate for receiving the second signal and a source connected to the grounding signal.

14. The storage system of claim 13 , wherein the first logic circuit comprises:
a first PMOS transistor, having a gate for receiving the fourth si

Assignees

• Changxin Memory Tech Inc

Inventors

• Ji Kangling
• He Jun
• Gong Yuanyuan
• Ying Zhan

Classifications

• G11C29/4401 Primary

  for self repair · CPC title

• G11C29/12005

  comprising voltage or current generators · CPC title

• G11C29/18

  Address generation devices; Devices for accessing memories, e.g. details of addressing circuits · CPC title

• H03K19/21 Primary

  EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical · CPC title

• G11C2029/1802

  Address decoder · CPC title