Generating ECC values for byte-write capable registers

Patent metadata

Field	Value
Publication number	US-9985656-B2
Application number	US-201514868544-A
Country	US
Kind code	B2
Filing date	Sep 29, 2015
Priority date	Sep 1, 2015
Publication date	May 29, 2018
Grant date	May 29, 2018

Abstract

Embodiments described herein include a computing system that permits partial writes into a memory element—e.g., a register on a processor. For example, the data to be written into the memory element may be spread across multiple sources. The register may receive data from two different sources at different times and perform two separate partial write commands to store the data. Embodiments herein generate an ECC value for each of the partial writes. That is, when storing the data of the first partial write, the computing system generates a first ECC value for the data in the first partial write and stores this value in the memory element. Later, when performing the second partial write, the computing system generates a second ECC value for this data which is also stored in the memory element.

First claim

What is claimed is:

1. A method for managing a memory including a plurality of registers, each register including a data entry, a first ECC entry, and a second ECC entry, the method comprising:
in response to receiving a first partial write request:
generating a first ECC value using data in the first partial write request, wherein at least one of a plurality of bits of the first ECC value is an invalid data bit, and
storing, in a first register of the plurality of registers, (i) the first ECC value in the first ECC entry and (ii) the data of the first partial write request in the data entry, wherein the data of the first partial write request only partially fills the data entry; and

in response to receiving a second partial write request:
generating a second ECC value using data in the second partial write request, wherein at least one of a plurality of bits of the second ECC value is an invalid data bit, and
storing, in the first register, (i) the second ECC in the second ECC entry and (ii) the data of the second partial write request in the data entry, wherein performing the first and second partial write requests fills the data entry without performing a read-modify-write.

2. The method of claim 1 , wherein valid bits of the plurality of bits of the first ECC value each correspond to a respective byte of the data in the first partial write request, and valid bits of the plurality of bits of the second ECC value each correspond to a respective byte of the data in the second partial write request.

3. The method of claim 1 , wherein the first ECC value has a total number of invalid bits that is different than a total number of invalid bits in the second ECC value.

4. The method of claim 1 , wherein the memory comprises a register file within a processor.

5. A method for managing a memory including a plurality of registers, each register including a data entry, a first ECC entry, and a second ECC entry, the method comprising:
in response to receiving a first partial write request, storing, in a first register of the plurality of registers, (i) a first ECC value generated using data in the first partial write request in the first ECC entry and (ii) the data of the first partial write request in the data entry, wherein the data of the first partial write request only partially fills the data entry;
in response to receiving a second partial write request, storing, in the first register, (i) a second ECC value generated using data in the second partial write request in the second ECC entry and (ii) the data of the second partial write request in the data entry, wherein performing the first and second partial write requests fills the data entry without performing a read-modify-write;
in response to receiving a request to read the data entry of the first register, determining if the data entry is partially full; and
upon determining the data entry is partially full, generating a combined ECC value by XORing the first ECC value with the second ECC value, wherein one of the first and second ECC values is filled with zeros.

6. The method of claim 5 , further comprising:
in response to the request to read the data entry of the first register, generating a test ECC value based on data stored in the data entry; and
comparing the test ECC value to the combined ECC value.

Assignees

• IBM

Inventors

• Jeganathan Dhivya
• Nguyen Dung Q
• Paredes Jose A
• Terry David R
• Thompto Brian W

Classifications

• H03M13/2906 Primary

  using block codes (H03M13/2957 takes precedence) · CPC title

• G06F11/1056 Primary

  Updating check bits on partial write, i.e. read/modify/write · CPC title

• G11C2029/0411

  Online error correction · CPC title

• G06F11/1064

  in cache or content addressable memories · CPC title