Memory device to execute read operation using read target voltage

Patent metadata

Field	Value
Publication number	US-11990190-B2
Application number	US-202318332472-A
Country	US
Kind code	B2
Filing date	Jun 9, 2023
Priority date	Sep 16, 2016
Publication date	May 21, 2024
Grant date	May 21, 2024

Abstract

A memory device includes first and second memory strings, first and second word lines and a controller. The first memory string includes first and second memory cells, a first select transistor, a second select transistor, and a third select transistor between the first and second memory cells. The second memory string includes third and fourth memory cells, a fourth select transistor above the third memory cell, a fifth select transistor below the fourth memory cell, and a sixth select transistor between the third and fourth memory cells. The first word line is electrically connected to gates of the first and third memory cells. The second word line is electrically connected to gates of the second and fourth memory cells. The controller is configured to execute a read operation on one of the memory cells, the read operation including a first phase and a second phase after the first phase.

First claim

What is claimed is:

1. A memory device comprising:
a semiconductor substrate having a main surface extending in a first direction and a second direction crossing the first direction;
a bit line provided on a side of the main surface in a third direction that crosses the first direction and the second direction and extending the first direction;
a first semiconductor pillar electrically connected to the bit line and extending in the third direction, the first semiconductor pillar having a first joint portion at a position in the third direction;
a second semiconductor pillar electrically connected to the bit line and extending in the third direction, the second semiconductor pillar having a second joint portion at the same position with the first joint portion in the third direction;
a first conductive member extending in the second direction and intersecting the first semiconductor pillar, the first conductive member being provided between the first joint portion and the bit line;
a second conductive member extending in the second direction and intersecting the second semiconductor pillar, the first and second conductive members being at a same position in the third direction, the second conductive member being electrically disconnected from the first conductive member;
a third conductive member extending in the second direction and intersecting the first semiconductor pillar, the third conductive member being provided between the first joint portion and the semiconductor substrate in the third direction;
a fourth conductive member extending in the second direction and intersecting the second semiconductor pillar, the third and fourth conductive members being at a same position in the third direction, the fourth conductive member being electrically disconnected from the third conductive member;
a fifth conductive member extending in the second direction and intersecting the first semiconductor pillar, the fifth conductive member being provided between the first conductive member and the bit line;
a sixth conductive member extending in the second direction and intersecting the second semiconductor pillar, the fifth and sixth conductive members being at a same position in the third direction, the sixth conductive member being electrically connected to the fifth conductive member;
a seventh conductive member extending in the second direction and intersecting the first semiconductor pillar, the seventh conductive member being provided between the substrate and the first joint portion; and
an eighth conductive member extending in the second direction and intersecting the second semiconductor pillar, the seventh and eighth conductive members being at a same position in the third direction, the eighth conductive member being electrically connected to the seventh conductive member.

2. The memory device according to claim 1 , further comprising:
a ninth conductive member extending in the second direction and intersecting the first semiconductor pillar, the ninth conductive member being provided between the fifth conductive member and the bit line; and
a tenth conductive member extending in the second direction and intersecting the second semiconductor pillar, the ninth and tenth conductive members being at a same position in the third direction, the tenth conductive member being electrically disconnected from the ninth conductive member.

3. The memory device according to claim 2 , further comprising:
an eleventh conductive member extending in the second direction and intersecting the first semiconductor pillar, the eleventh conductive member being provided between the seventh conductive member and the substrate; and
a twelfth conductive member extending in the second direction and intersecting the second semiconductor pillar, the eleventh and twelfth conductive members being at a same position in the third direction, the twelfth conductive member being electrically disconnected from the eleventh conductive member.

4. The memory device according to claim 1 , wherein
the fifth conductive member is provided in plurality along the third direction, a lowermost one thereof facing the first conductive member, an uppermost one thereof facing the ninth conductive member,
the sixth conductive member is provided in plurality along the third direction, a lowermost one thereof facing the second conductive member, an uppermost one thereof facing the tenth conductive member,
the seventh conductive member is provided in plurality along the third direction, a lowermost one thereof facing the eleventh conductive member, an uppermost one thereof facing the third conductive member, and
the eighth conductive member is provided in plurality along the third direction, a lowermost one thereof facing the twelfth conductive member, an uppermost one thereof facing the fourth conductive member.

5. The memory device according to claim 4 , further comprising:
a first charge storage film surrounding the first semiconductor pillar; and
a second charge storage film surrounding the second semiconductor pillar.

6. The memory device according to claim 5 , wherein
intersections of the plurality of the fifth conductive members and the first semiconductor pillar function as first memory cells, respectively,
intersections of the plurality of the seventh conductive members and the first semiconductor pillar function as second memory cells, respectively,
intersections of the plurality of the sixth conductive members and the second semiconductor pillar function as third memory cells, respectively, and
intersections of the plurality of the eighth conductive members and the first semiconductor pillar function as fourth memory cells, respectively.

7. The memory device according to claim 6 , further comprising:
a third semiconductor pillar electrically connected to the bit line and extending in the third direction, the third semiconductor pillar having a third joint portion at the same position with the first joint portion in the third direction;
a third charge storage film surrounding the third semiconductor pillar;
a fourth semiconductor pillar electrically connected to the bit line and extending in the third direction, the fourth semiconductor pillar having a fourth joint portion at the same position with the first joint portion in the third direction;
a fourth charge storage film surrounding the fourth semiconductor pillar;
a thirteenth conductive member extending in the second direction and intersecting the third semiconductor pillar, the ninth and thirteenth conductive members being at a same position in the third direction, the thirteenth conductive member being electrically disconnected from the ninth conductive member; and
a fourteenth conductive member extending in the second direction and intersecting the fourth semiconductor pillar, the tenth and fourteenth conductive members being at a same position in the third direction, the fourteenth conductive member being electrically disconnected from the tenth conductive member.

8. The memory device according to claim 7 , wherein
the first conductive member intersects the third semiconductor pillar,
the third conductive member intersects the third semiconductor pillar,
the plurality of fifth conductive members intersect the third semiconductor pillar,
the plurality of seventh conductive members intersect the third semiconductor pillar,
the eleventh conductive member intersects the third semiconductor pillar,
the second conductive member intersects the fourth semiconductor pillar,
the fourth conductive member intersects the fourth semiconductor pillar,
the plurality of sixth conductive members intersect the fourth semiconductor pillar,
the plurality of eighth conductive members intersect the fourth semicon

Assignees

• Kioxia Corp

Inventors

• Maejima Hiroshi

Classifications

• G11C16/3427 Primary

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/08 Primary

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/16

  for erasing blocks, e.g. arrays, words, groups · CPC title