Memory device to execute read operation using read target voltage

Patent metadata

Field	Value
Publication number	US-10699792-B2
Application number	US-201816210537-A
Country	US
Kind code	B2
Filing date	Dec 5, 2018
Priority date	Sep 16, 2016
Publication date	Jun 30, 2020
Grant date	Jun 30, 2020

Abstract

A memory device includes first and second memory strings, first and second word lines and a controller. The first memory string includes first and second memory cells, a first select transistor, a second select transistor, and a third select transistor between the first and second memory cells. The second memory string includes third and fourth memory cells, a fourth select transistor above the third memory cell, a fifth select transistor below the fourth memory cell, and a sixth select transistor between the third and fourth memory cells. The first word line is electrically connected to gates of the first and third memory cells. The second word line is electrically connected to gates of the second and fourth memory cells. The controller is configured to execute a read operation on one of the memory cells, the read operation including a first phase and a second phase after the first phase.

First claim

What is claimed is:

1. A memory device comprising:
a bit line;
a first memory string including:
a first upper select transistor connected to the bit line;
a first upper memory cell transistor disposed below the first upper select transistor;
a first middle-upper select transistor disposed below the first upper memory cell transistor;
a first middle-lower select transistor disposed below the first middle-upper select transistor;
a first lower memory cell transistor disposed below the first middle-lower select transistor; and
a first lower select transistor disposed below the first lower memory cell transistor;

a second memory string including:
a second upper select transistor connected to the bit line;
a second upper memory cell transistor disposed below the second upper select transistor;
a second middle-upper select transistor disposed below the second upper memory cell transistor;
a second middle-lower select transistor disposed below the second middle-upper select transistor;
a second lower memory cell transistor disposed below the second middle-lower select transistor; and
a second lower select transistor disposed below the second lower memory cell transistor;

an upper word line electrically connected to a gate of the first upper memory cell transistor and a gate of the second upper memory cell transistor;
a lower word line electrically connected to a gate of the first lower memory cell transistor and a gate of the second lower memory cell transistor; and
a controller configured to execute a read operation, the read operation including a first phase and a second phase after the first phase,
wherein when a read target is the first upper memory cell transistor,
during the first phase, a first voltage is applied to the first upper select transistor, the first middle-upper select transistor, and the second upper select transistor, and a second voltage lower than the first voltage is applied to the second middle-lower select transistor and the second lower select transistor, and
during the second phase, the first voltage is applied to the first upper select transistor, the first middle-upper select transistor, the first middle-lower select transistor, and the first lower select transistor, the second voltage is applied to the second upper select transistor, the second middle-upper select transistor, and the second lower select transistor, a read target voltage is applied to the upper word line, and a read pass voltage is applied to the lower word line.

2. The memory device according to claim 1 , wherein when the read target is the first upper memory cell transistor,
during the first phase, the first voltage is further applied to the first middle-lower select transistor, the first lower select transistor, and the second middle-lower select transistor.

3. The memory device according to claim 1 , wherein when the read target is the first upper memory cell transistor,
during the first phase, the first voltage is applied to the first upper select transistor, the first middle-upper select transistor, and the second upper select transistor, and the second voltage is applied to the second middle-lower select transistor and the second lower select transistor, and
during the second phase, the first voltage is applied to the first upper select transistor, the first middle-upper select transistor, the first middle-lower select transistor, and the first lower select transistor, the second voltage is applied to the second upper select transistor, the second middle-upper select transistor, and the second lower select transistor, a read target voltage is applied to the upper word line, and a read pass voltage is applied to the lower word line.

4. The memory device according to claim 1 , wherein
the controller is further configured to execute a program operation, and
the read operation is carried out after the program operation as a part of a verification operation.

5. The memory device according to claim 1 , wherein the second voltage is ground voltage.

6. The memory device according to claim 1 , wherein the second voltage is higher than ground voltage.

7. The memory device according to claim 1 , further comprising:
a third memory string including:
a third upper select transistor connected to the bit line;
a third upper memory cell transistor disposed below the third upper select transistor;
a third middle-upper select transistor disposed below the third upper memory cell transistor;
a third middle-lower select transistor disposed below the third middle-upper select transistor;
a third lower memory cell transistor disposed below the third middle-lower select transistor; and
a third lower select transistor disposed below the third lower memory cell transistor; and

a fourth memory string including:
a fourth upper select transistor connected to the bit line;
a fourth upper memory cell transistor disposed below the fourth upper select transistor;
a fourth middle-upper select transistor disposed below the fourth upper memory cell transistor;
a fourth middle-lower select transistor disposed below the fourth middle-upper select transistor;
a fourth lower memory cell transistor disposed below the fourth middle-lower select transistor; and
a fourth lower select transistor disposed below the fourth lower memory cell transistor, wherein

the upper word line is further electrically connected to a gate of the third upper memory cell transistor and a gate of the fourth upper memory cell transistor, and
the lower word line is further electrically connected to a gate of the third lower memory cell transistor and a gate of the fourth lower memory cell transistor.

8. The memory device according to claim 7 , further comprising:
a first upper select gate line electrically connected to a gate of the first upper select transistor;
a second upper select gate line electrically connected to a gate of the second upper select transistor;
a third upper select gate line electrically connected to a gate of the third upper select transistor;
a fourth upper select gate line electrically connected to a gate of the fourth upper select transistor;
a first middle-upper select gate line electrically connected to a gate of the first middle-upper select transistor and a gate of the third middle-upper select transistor;
a second middle-upper select gate line electrically connected to a gate of the second middle-upper select transistor and a gate of the fourth middle-upper select transistor;
a first middle-lower select gate line electrically connected to a gate of the first middle-lower select transistor and a gate of the third middle-lower select transistor;
a second middle-lower select gate line electrically connected to a gate of the second middle-lower select transistor and a gate of the fourth middle-lower select transistor;
a first lower select gate line electrically connected to a gate of the first lower select transistor and a gate of the third lower select transistor; and
a second lower select gate line electrically connected to a gate of the second lower select transistor and a gate of the fourth lower select transistor.

9. The memory device according to claim 1 , wherein
the first memory string further includes a first middle-upper-inside dummy transistor and a first middle-lower-inside dummy transistor disposed between the first middle-upper select transistor and the first middle-lower select transistor, and
the second memory string further includes a second middle-upper-inside dummy transistor and a second middle-lower-inside dummy transistor disposed between the second middle-upper select transistor and the second middle-lower select transistor.

10. The memory device according

Assignees

• Toshiba Memory Corp

Inventors

• Maejima Hiroshi

Classifications

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/08 Primary

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/32

  Timing circuits · CPC title

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title