Memory device to execute read operation using read target voltage

Patent metadata

Field	Value
Publication number	US-10186323-B2
Application number	US-201815902399-A
Country	US
Kind code	B2
Filing date	Feb 22, 2018
Priority date	Sep 16, 2016
Publication date	Jan 22, 2019
Grant date	Jan 22, 2019

Abstract

A memory device includes first and second memory strings, first and second word lines and a controller. The first memory string includes first and second memory cells, a first select transistor, a second select transistor, and a third select transistor between the first and second memory cells. The second memory string includes third and fourth memory cells, a fourth select transistor above the third memory cell, a fifth select transistor below the fourth memory cell, and a sixth select transistor between the third and fourth memory cells. The first word line is electrically connected to gates of the first and third memory cells. The second word line is electrically connected to gates of the second and fourth memory cells. The controller is configured to execute a read operation on one of the memory cells, the read operation including a first phase and a second phase after the first phase.

First claim

What is claimed is:

1. A memory device comprising:
a first memory string including a first memory cell, a second memory cell, a first select transistor above the first memory cell, a second select transistor below the second memory cell, and a third select transistor between the first memory cell and the second memory cell;
a second memory string including a third memory cell, a fourth memory cell, a fourth select transistor above the third memory cell, a fifth select transistor below the fourth memory cell, and a sixth select transistor between the third memory cell and the fourth memory cell;
a first word line electrically connected to a gate of the first memory cell and a gate of the third memory cell;
a second word line electrically connected to a gate of the second memory cell and a gate of the fourth memory cell; and
a controller configured to execute a read operation on one of the memory cells, the read operation including a first phase and a second phase after the first phase, wherein
when a read target is one of the first memory cell and the second memory cell,
during the first phase, a first voltage is applied to one of the first select transistor and the second select transistor, the third select transistor, and one of the fourth select transistor and the fifth select transistor, and a second voltage lower than the first voltage is applied to the sixth select transistor and the other one of the fourth select transistor and the fifth select transistor, and
during the second phase, the first voltage is applied to the first select transistor, the second select transistor and the third select transistor, and the second voltage is applied to the fourth select transistor, the fifth select transistor, and the sixth select transistor.

2. The device according to claim 1 , wherein, when the read target is the first memory cell,
during the first phase, the first voltage is applied to the first, second, third, and fourth select transistors, and the second voltage is applied to the fifth and sixth select transistors, and
during the second phase, the second voltage is applied to the fourth, fifth, and sixth select transistors, and a read target voltage is applied to the first word line.

3. The device according to claim 1 , wherein, when the read target is the second memory cell,
during the first phase, the first voltage is applied to the first, second, third, and fifth select transistors, and the second voltage is applied to the fourth and sixth select transistors, and
during the second phase, the second voltage is applied to the fourth, fifth, and sixth select transistors, and a read target voltage is applied to the second word line.

4. The device according to claim 1 , wherein, when the read target is the first memory cell,
during the first phase,
the first voltage is applied to the first, second, and fourth select transistors, and
the second voltage is applied to the fifth and sixth select transistors, and during the second phase,
the first voltage is applied to the third select transistor,
the second voltage is applied to the fourth, fifth, and sixth select transistors, and
a read target voltage is applied to the first word line.

5. The device according to claim 1 , wherein, when the read target is the second memory cell,
during the first phase,
the first voltage is applied to the second, third, and fifth select transistors, and
the second voltage is applied to the fourth and sixth select transistors, and during the second phase,
the first voltage is applied to the first select transistor,
the second voltage is applied to the fourth, fifth, and sixth select transistors, and
a read target voltage is applied to the second word line.

6. The device according to claim 1 , wherein
the controller is further configured to execute a program operation, and
the read operation is carried out after the program operation as a part of a verification operation.

7. The device according to claim 1 , wherein
during the first phase, the first voltage is applied to the second select transistor, and
during the second phase, the voltage applied to one of the first and second select transistors transitions from the first voltage to the second voltage, and thereafter transitions from the second voltage to the first voltage.

8. The device according to claim 1 , wherein the second voltage is ground voltage.

9. The device according to claim 1 , wherein the second voltage is higher than ground voltage.

10. The device according to claim 1 , wherein
the first memory string further includes:
a fifth memory cell below the third select transistor, and
a seventh select transistor below the fifth memory cell and above the second memory cell,

the second memory string further includes:
a sixth memory cell below the fifth select transistor, and
an eighth select transistor below the sixth memory cell and above the fourth memory cell, and

a gate of the fifth memory cell and a gate of the sixth memory cell are electrically connected via a third word line.

11. The device according to claim 1 , wherein, when the read target is the first memory cell,
during the first phase,
the first voltage is applied to the first, second, third, fourth, and seventh select transistors, and
the second voltage is applied to the fifth, sixth, and eighth select transistors, and

during the second phase,
the second voltage is applied to the fourth, fifth, sixth, and eighth select transistors, and
a read target voltage is applied to the first word line.

12. A memory device comprising:
a first memory string including a first memory cell, a second memory cell, a first select transistor above the first memory cell, a second select transistor below the second memory cell, and third and fourth select transistors between the first and second memory cells;
a second memory string including a third memory cell, a fourth memory cell, a fifth select transistor above the third memory cell, a sixth select transistor below the fourth memory cell, and seventh and eighth select transistors between the third and fourth memory cells;
a first word line electrically connected to gates of the first and third memory cells;
a second word line electrically connected to gates of the second and fourth memory cells; and
a controller configured to execute a read operation on one of the memory cells, the read operation including a first phase and a second phase, wherein
when a read target is one of the first and second memory cells,
during the first phase, a first voltage is applied to the first, second, third, and fourth select transistors, one of the fifth and sixth select transistors, and one of the seventh and eighth select transistors, and a second voltage lower than the first voltage is applied to the other one of the fifth and sixth select transistors and the other one of the seventh and eighth select transistors, and
during the second phase, the second voltage is applied to the fifth and sixth select transistors, and the other one of the seventh and eighth select transistors, and the voltage applied to said one of the seventh and eighth select transistors is maintained at the first voltage.

13. The device according to claim 12 , wherein, when the read target is the first memory cell,
during the first phase, the first voltage is applied to the first, second, third, fourth, fifth, and eighth select transistors, and the second voltage is applied to the sixth and seventh select transistors, and
during the second phase, the second voltage is applied to the fifth, sixth, and seventh select transistors, and a read target voltage is applied to the first word line.

Assignees

• Toshiba Memory Corp

Inventors

• Maejima Hiroshi

Classifications

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C16/08 Primary

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/32

  Timing circuits · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/16

  for erasing blocks, e.g. arrays, words, groups · CPC title