Read-write data translation technique of asynchronous clock domains

Patent metadata

Field	Value
Publication number	US-10164758-B2
Application number	US-201615386342-A
Country	US
Kind code	B2
Filing date	Dec 21, 2016
Priority date	Nov 30, 2016
Publication date	Dec 25, 2018
Grant date	Dec 25, 2018

Abstract

An electronic system includes transmitting circuitry of a first clock domain and receiving circuitry of a second domain. The transmitting circuitry re-times a digital input signal with rising edges of a clocking signal of the first clock domain when a phase of the clocking signal of the first clock domain leads a phase of a clocking signal associated with the digital input signal. Otherwise, the transmitting circuitry re-times the digital input signal with falling edges of the clocking signal of the first clock domain when the phase of the clocking signal of the first clock domain does not lead the phase of the clocking signal associated with a digital input signal. The receiving circuitry receives the re-timed digital input signal from the transmitting circuitry. Thereafter, the receiving circuitry re-times the re-timed digital input signal with rising edges of a phase of a clocking signal associated with the re-timed digital input signal when the phase of the clocking signal associated with the re-timed digital input signal leads a phase of a clocking signal of the second clock domain. Otherwise, the receiving circuitry re-times the re-timed digital input signal with falling edges of the phase of a clocking signal associated with the re-timed digital input signal when the phase of the clocking signal associated with the re-timed digital input signal does not lead the phase of a clocking signal of the second clock domain.

First claim

What is claimed is:

1. A transmitting circuitry of a first clock domain, the transmitting circuitry comprising:
transmitter-edge-detect (TED) circuitry configured to:
determine whether a digital input signal is to be re-timed with a rising edge or a falling edge of a clocking signal of the first clock domain, and
provide a clocking signal selection at a first logical level when the digital input signal is to be re-timed with the falling edge when a phase of a second clocking signal associated with the digital input signal is lagging a phase of the clocking signal or at a second logical level when the digital input signal is to be re-timed with the rising edge when the phase of the second clocking signal is leading the phase of the clocking signal; and

transmitter-cross-domain (TCD) circuitry configured to:
re-time the digital input signal in accordance with the falling edge when the clocking signal selection is at the first logical level, and
re-time the digital input signal in accordance with the rising edge when the clocking signal selection is at the second logical level.

2. The transmitting circuitry of claim 1 , wherein the TED circuitry is further configured to determine the digital input signal is to be re-timed with the rising edge when the phase of the second clocking signal is leading the phase of the clocking signal by at least a delay factor.

3. The transmitting circuitry of claim 1 , wherein the TED circuitry comprises:
digital delay circuitry configured to delay the clocking signal by a delay factor to provide a delayed clocking signal of the first clock domain; and
a flip-flop configured to re-time the second clocking signal in accordance with the delayed clocking signal to provide the clocking signal selection.

4. The transmitting circuitry of claim 1 , wherein the TCD circuitry comprises:
a flip-flop configured to re-time the digital input signal in accordance with the clocking signal to provide a re-timed digital input signal;
a rising edge signal processing path configured to re-time the re-timed digital input signal in accordance with the rising edge to provide a re-timed rising edge digital input signal;
a falling edge signal processing path configured to re-time the re-timed digital input signal in accordance with the falling edge to provide a re-timed falling edge digital input signal; and
selection circuitry configured to select the re-timed falling edge digital input signal when the clocking signal selection is at the first logical level or the re-timed rising edge digital input signal when the clocking signal selection is at the second logical level.

5. The transmitting circuitry of claim 4 , wherein the rising edge signal processing path comprises:
a flip-flop configured to re-time the re-timed digital input signal in accordance with the rising edge to provide the re-timed rising edge digital input signal.

6. The transmitting circuitry of claim 4 , wherein the falling edge signal processing path comprises:
a first flip-flop configured to re-time the re-timed digital input signal in accordance with the failing edge to provide a falling edge digital input signal; and
a second flip-flop configured to re-time the falling edge digital input signal in accordance with the rising edge to provide the re-timed falling edge digital input signal.

7. The transmitting circuitry of claim 4 , further comprising:
multiplexing circuitry configured to:
perform a parallel-to-serial conversion on one of the selected re-timed falling edge digital input signal or the selected re-timed rising edge digital input signal to provide a transmitting digital output signal, and
provide the transmitting digital output signal to receiving circuitry of a second clock domain.

8. A receiving circuitry of a first clock domain, the receiving circuitry comprising:
receiver-edge-detect (RED) circuitry configured to:
receive a digital input signal from transmitting circuitry of a second clock domain,
determine whether the digital input signal is to be re-timed with a rising edge or a falling edge of a clocking signal of the first clock domain, and
provide a clocking signal selection at a first logical level when the digital input signal is to be re-timed with the rising edge or at a second logical level when the digital input signal is to be re-timed with the falling edge; and

receiver-cross-domain (RCD) circuitry configured to;
re-time the digital input signal in accordance with the rising edge when the clocking signal selection is at the first logical level, and
re-time the digital input signal in accordance with the falling edge when the clocking signal selection is at the second logical level.

9. The receiving circuitry of claim 8 , wherein the RED circuitry is further configured to determine the digital input signal is to be re-timed with the falling edge when a phase of the clocking signal is leading a phase of a second clocking signal associated with the digital input signal.

10. The receiving circuitry of claim 9 , wherein the RED circuitry is further configured to determine the digital input signal is to be re-timed with the falling edge when the phase of the clocking signal is leading the phase of the second clocking signal by at least a delay factor.

11. The receiving circuitry of claim 10 , wherein the RED circuitry comprises:
digital delay circuitry configured to delay the clocking signal by the delay factor to provide a delayed clocking signal; and
a flip-flop configured to re-time the clocking signal in accordance with the delayed clocking signal to provide the clocking signal selection.

12. The receiving circuitry of claim 8 , wherein the RCD circuitry comprises:
a rising edge signal processing path configured to re-time the digital input signal in accordance with the rising edge to provide a re-timed rising edge digital input signal;
a falling edge signal processing path configured to re-time the digital input signal in accordance with the falling edge to provide a re-timed falling edge digital input signal;
selection circuitry configured to select the re-timed rising edge digital input signal when the clocking signal selection is at the first logical level or the re-timed falling edge digital input signal when the clocking signal selection is at the second logical level; and
a flip-flop configured to re-time the selected re-timed falling edge digital input signal or the selected re-timed rising edge digital input signal in accordance with the clocking signal to provide a re-timed digital input signal.

13. The receiving circuitry of claim 12 , wherein the rising edge signal processing path comprises:
a flip-flop configured to re-time the digital input signal in accordance with the rising edge to provide the re-timed rising edge digital input signal.

14. The receiving circuitry of claim 12 , wherein the falling edge signal processing path comprises:
a flip-flop configured to re-time the digital input signal in accordance with the falling edge to provide the re-timed falling edge digital input signal.

15. A method for transmitting a digital signal between a first clock domain and a second clock domain, the method comprising:
determining, by a first circuit of the first clock domain, whether the digital input signal is to be re-timed with a rising edge or a falling edge of a first clocking signal of the first clock domain;
providing, by the first circuit of the first clock domain, a first clocking signal selection at a first logical level when the digital input signal is to be re-timed with the falling edge of the first clocking signal or at a second logical level wh

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semicondcutor Mfg Co Ltd

Inventors

• Yang Shu-Chun
• Lin Mu-Shan
• Huang Wen-Hung

Classifications

• H04L7/0091 Primary

  Transmitter details · CPC title

• H04L7/0045 Primary

  Correction by a latch cascade · CPC title

• G06F13/00

  Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units (interface circuits for specific input/output devices G06F3/00 {; multiprogram control therefor  G06F9/46}; multiprocessor systems  G06F15/16 ) · CPC title

• H04L7/0008 Primary

  Synchronisation information channels, e.g. clock distribution lines · CPC title

• G06F1/12 Primary

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title