Nonvolatile memory apparatus for mitigating read disturbance and system using the same

Patent metadata

Field	Value
Publication number	US-11984159-B2
Application number	US-202117472179-A
Country	US
Kind code	B2
Filing date	Sep 10, 2021
Priority date	Jun 21, 2019
Publication date	May 14, 2024
Grant date	May 14, 2024

Abstract

A nonvolatile memory apparatus may include a memory cell, a bit line control circuit, and a word line control circuit. The memory cell may be coupled between a global bit line and a global word line. During a read operation, the bit line control circuit may provide a first high voltage to the global bit line and provide a second high voltage to the global bit line when snapback of the memory cell occurs. During the read operation, the word line control circuit may provide a second read supply voltage to the global word line and provide an anneal supply voltage to the global word line when snapback of the memory cell occurs.

First claim

What is claimed is:

1. A nonvolatile memory apparatus comprising:
a memory cell coupled between a global bit line and a global word line;
a bit line control circuit configured to provide a first high voltage to the global bit line based on a read signal and to provide a second high voltage to the global bit line based on a first control signal, and configured to control a first current to flow through the global bit line based on the read signal and to control a second current to flow through the global bit line based on the first control signal;
a word line control circuit configured to provide a first low voltage to the global word line based on the read signal and to provide a second low voltage to the global word line based on a second control signal; and
a sense amplifier configured to sense a voltage level of the global bit line to determine whether snapback of the memory cell has occurred, and configured to generate the first and second control signals when the snapback of the memory cell has occurred,
wherein the second current is larger than the first current, and the second current comprises an amount of current capable of setting a resistance state of the memory cell to a low resistance state,
wherein the second high voltage has a higher voltage level than the first high voltage.

2. The nonvolatile memory apparatus according to claim 1 , wherein the bit line control circuit comprises:
a read current circuit configured to supply a first read supply voltage as the first high voltage to the global bit line, and control the first current to flow through the global bit line, based on the read signal; and
an anneal current circuit configured to supply an anneal high voltage, which has a higher voltage level than the first read supply voltage, as the second high voltage to the global bit line, and control the second current to flow through the global bit line, based on the first control signal.

3. The nonvolatile memory apparatus according to claim 2 , wherein the read current circuit comprises:
a precharge circuit configured to supply the first read supply voltage to the global bit line based on a precharge signal; and
a first current mirror comprising a first current source for supplying the first current, and configured to control the first current to flow through the global bit line, based on a read pulse signal generated from the read signal.

4. The nonvolatile memory apparatus according to claim 3 , wherein the anneal current circuit comprises a second current mirror comprising a second current source for supplying the second current, and configured to control the second current to flow through the global word line when the first control signal is enabled.

5. The nonvolatile memory apparatus according to claim 1 , wherein the word line control circuit comprises:
a read voltage supply circuit configured to generate the first low voltage by raising the voltage level of a second read supply voltage, and supply the first low voltage to the global word line, based on a clamping signal and a read enable signal generated from the read signal; and
a bypass circuit configured to generate the second low voltage from the second read supply voltage, and supply the second low voltage to the global word line, based on the second control signal.

6. The nonvolatile memory apparatus according to claim 1 , wherein the word line control circuit comprises:
a read voltage supply circuit configured to generate the first low voltage by raising the voltage level of a second read supply voltage, and supply the first low voltage to the global word line, based on a clamping signal and a read enable signal generated from the read signal; and
an anneal voltage supply circuit configured to generate the second low voltage from an anneal low voltage having a higher voltage level than the second read supply voltage, and supply the second low voltage to the global word line, based on the second control signal.

7. The nonvolatile memory apparatus according to claim 1 , wherein the sense amplifier generates the first and second control signals when the voltage level of the global bit line is lower than the voltage level of a reference voltage.

8. The nonvolatile memory apparatus according to claim 1 , wherein the sense amplifier disables the first control signal before disabling the second control signal.

9. The nonvolatile memory apparatus according to claim 1 , wherein the memory cell is coupled between a bit line and a word line,
wherein the nonvolatile memory apparatus further comprises:
a voltage level shifter configured to raise the voltage level of a bit line selection signal;
a column selection switch configured to couple the global bit line to the bit line based on an output of the voltage level shifter; and
a row selection switch configured to couple the global word line to the word line based on a word line selection signal.

10. An operation method of a nonvolatile memory apparatus, the method comprising:
selecting a bit line to couple a memory cell to a global bit line, and selecting a word line to couple the memory cell to a global word line;
applying a read voltage across the memory cell by applying a first high voltage to the global bit line and applying a first low voltage to the global word line, such that a first current flows through the memory cell;
sensing a voltage level of the global bit line to determine whether snapback of the memory cell has occurred; and
applying an anneal voltage across the memory cell by applying a second high voltage to the global bit line and applying a second low voltage to the global word line, such that a second current, capable of setting the memory cell to a low resistance state, flows through the memory cell, when the snapback of the memory cell has occurred,
wherein the second current is larger than the first current,
wherein the anneal voltage has a higher voltage level than the read voltage.

11. The operation method according to claim 10 , wherein the second high voltage has a higher voltage level than the first high voltage.

12. The operation method according to claim 10 , wherein the second low voltage has a lower voltage level than the first low voltage.

13. The operation method according to claim 10 , wherein selecting the bit line to couple the memory cell to the global bit line comprises:
generating a column selection signal based on a column address signal; and
coupling the bit line to the global bit line based on the column selection signal.

14. The operation method according to claim 13 , wherein selecting the word line to couple the memory cell to the global word line comprises:
generating a row selection signal based on a row address signal; and
coupling the word line to the global word line based on the row selection signal.

15. The operation method according to claim 14 , further comprising:
raising the voltage level of the column selection signal after generating the column selection signal, or lowering the voltage level of the row selection signal after generating the row selection signal.

16. An operation method of a nonvolatile memory apparatus, the method comprising:
selecting a bit line to couple a memory cell to a global bit line, and selecting a word line to couple the memory cell to a global word line;
applying a read voltage across the memory cell and causing a first current to flow through the memory cell;
sensing a voltage level of the global bit line to determine whether a snapback of the memory cell has occurred; and
applying an anneal voltage across the memory cell and causing a second current to

Assignees

• Sk Hynix Inc

Inventors

• Park Moo Hui
• Kang Seok Joon
• Cheon Jun Ho

Classifications

• G11C8/14

  Word line organisation; Word line lay-out · CPC title

• G11C7/18

  Bit line organisation; Bit line lay-out · CPC title

• G11C13/0033 Primary

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title

• G11C13/0026

  Bit-line or column circuits · CPC title