Drift detection in timing signal forwarded from memory controller to memory device

Patent metadata

Field	Value
Publication number	US-11983031-B2
Application number	US-202318206867-A
Country	US
Kind code	B2
Filing date	Jun 7, 2023
Priority date	Oct 26, 2011
Publication date	May 14, 2024
Grant date	May 14, 2024

Abstract

A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.

First claim

What is claimed is:

1. A memory controller comprising:
a phase lock loop to generate a first timing signal having a first frequency;
a multiplexor connected to the phase lock loop, the multiplexor to receive the first timing signal from an output of the phase lock loop and a second timing signal having a second frequency that is less than the first frequency, the multiplexor to output one of the first timing signal or the second timing signal;
an interface circuit connected the multiplexor, the interface circuit to output, to a memory device, one of the first timing signal or the second timing, and the interface circuit to receive from the memory device information indicative of a phase delay, occurring on the second timing signal, associated with timing drift in the memory device; and
a phase mixer circuit connected to the multiplexor, the phase mixer circuit to adjust a phase of the first timing signal based on the information indicative of the phase delay.

2. The memory controller of claim 1 , wherein the interface circuit outputs the second timing signal to the memory device during a power down event or calibration event of the memory device.

3. The memory controller of claim 1 , wherein the multiplexor outputs the first timing signal to the interface circuit for a data transfer operation between the memory controller and the memory device.

4. The memory controller of claim 1 , further comprising:
a drift tracking circuit connected to the interface circuit, the drift tracking circuit to receive the information from the interface circuit, and the drift tracking circuit to output to an input of the phase mixer circuit a phase adjustment control signal that is indicative of an amount of phase adjustment based on the information,
wherein the phase mixer circuit receives the first timing signal from the output of the multiplexor and wherein the phase mixer circuit receives the phase adjustment control signal from an output of the drift tracking circuit, and wherein the phase mixer circuit adjusts a phase of the first timing signal according to an amount of phase adjustment indicated in the phase adjustment control signal.

5. The memory controller of claim 4 , wherein the phase mixer circuit comprises:
a transmission phase mixer to receive the first timing signal from the output of the multiplexor and the transmission phase mixer to receive the phase adjustment control signal from the output of the drift tracking circuit, the transmission phase mixer to output a transmit clock signal that is based the first timing signal with the adjusted phase, the transmit clock signal to time transmission of data to be written to the memory device; and
a receiver phase mixer to receive the first timing signal from the output of the multiplexor and the receiver phase mixer to receive the phase adjustment control signal from the output of the drift tracking circuit, and the receiver phase mixer to output a receive clock signal that is based on the first timing signal with the adjusted phase, the receive clock to time reception of data read from the memory device.

6. The memory controller of claim 1 , wherein the information includes a digital value indicative of the phase delay occurring on the second timing signal.

7. The memory controller of claim 1 , wherein the second frequency is a fraction of the first frequency.

8. A method of operating a memory controller, the method comprising:
generating, by a phase lock loop of the memory controller, a first timing signal having a first frequency;
receiving, by a multiplexor connected to the phase lock loop, the first timing signal from the multiplexor and a second timing signal having a second frequency that is less than the first frequency,
outputting, by an interface circuit connected to the multiplexor, the first timing signal or the second timing signal to a memory device;
receiving, by the interface circuit, information indicative of a phase delay occurring on the second timing signal associated with timing drift in the memory device; and
adjusting, by a phase mixer circuit, a phase of the first timing signal based on the information indicative of the phase delay occurring on the second timing signal.

9. The method of claim 8 , wherein the second timing signal is output to the memory device during a power down event or calibration event of the memory device.

10. The method of claim 8 , wherein the first timing signal is output to the interface circuit for a data transfer operation between the memory controller and the memory device.

11. The method of claim 8 , further comprising:
receiving, by a drift tracking circuit that is connected to the interface circuit, the information from the interface circuit;
outputting, by the drift tracking circuit, a phase adjustment control signal that is indicative of an amount of phase adjustment based on the information to the phase mixer circuit; and
adjusting, by the phase mixer circuit, a phase of the first timing signal according to the amount of phase adjustment indicated in the phase adjustment control signal.

12. The method of claim 11 , further comprising:
receiving, by a transmission phase mixer included in the phase mixer circuit, the first timing signal from the multiplexor and the phase adjustment control signal from the drift tracking circuit, and outputting a transmit clock signal that is based the first timing signal with the adjusted phase, the transmit clock signal for transmitting data for writing to the memory device; and
receiving, by a receiver phase mixer included in the phase mixer circuit, the first timing signal output from the multiplexor and the phase adjustment control signal from the drift tracking circuit, and outputting a receive clock signal that is based the first timing signal with the adjusted phase, the receive clock for receiving data read from the memory device.

13. The method of claim 8 , wherein the information includes a digital value indicative of the phase delay occurring on the second timing signal.

14. The method of claim 8 , wherein the second timing signal is a fraction of the first timing signal.

15. A memory controller comprising:
means for generating a first timing signal having a first frequency;
means for receiving the first timing signal and a second timing signal, the second timing signal having a second frequency that is less than the first frequency;
means for outputting the first timing signal or the second timing signal to a memory device; and
means for adjusting a phase of the first timing signal based on information indicative of a phase delay occurring on the second timing signal.

16. The memory controller of claim 15 , wherein the second timing signal is output to the memory device during a power down event or calibration event of the memory device.

17. The memory controller of claim 15 , wherein the first timing signal is output for a data transfer operation between the memory controller and the memory device.

18. The memory controller of claim 15 , further comprising:
means for outputting to the means for adjusting the phase of the first timing signal a phase adjustment control signal that is indicative of an amount of phase adjustment based on the information,
wherein the means for adjusting the adjusts a phase of the first timing signal according to an amount of phase adjustment indicated in the phase adjustment control signal and the first timing signal.

19. The memory controller of claim 15 , wherein the information includes a digital value indicative of the phase delay occurr

Assignees

• Rambus Inc

Inventors

• Kim Jun
• Chau Pak Shing
• Richardson Wayne S

Classifications

• G06F1/08 Primary

  Clock generators with changeable or programmable clock frequency · CPC title

• G06F1/10

  Distribution of clock signals {, e.g. skew} · CPC title

• G06F13/1673

  using buffers · CPC title

• G06F13/1689 Primary

  Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title

• H03L7/07

  using several loops, e.g. for redundant clock signal generation · CPC title