Levelization of memory interface for communicating with multiple memory devices

Patent metadata

Field	Value
Publication number	US-9330034-B2
Application number	US-201113582043-A
Country	US
Kind code	B2
Filing date	Mar 30, 2011
Priority date	Apr 14, 2010
Publication date	May 3, 2016
Grant date	May 3, 2016

Abstract

In a memory system in which a system clock signal is forwarded from the memory controller to multiple memory devices, the phase of the system clock signal forwarded to the slower memory device is advanced relative to the system clock signal forwarded to the faster memory device by a phase corresponding to the skew on the data links corresponding to the memory devices. This causes the state machine of the slower memory device to change states and advance earlier than the state machine in the faster memory device, and as a result, the data read from both the slower memory device and the faster memory device are unskewed on the data links between the memory controller and the memory devices.

First claim

What is claimed is:

1. In a memory controller for controlling a plurality of memory devices including at least a first memory device and a second memory device, respectively, a method comprising:
determining a skew between timings when first data and second data are received from the first memory device and the second memory device, respectively, the first data read from the first memory device according to a first clock signal forwarded from the memory controller via a first communication channel and the second data read from the second memory device according to a second clock signal forwarded from the memory controller via a second communication channel; and
generating, by the memory controller, an advanced first clock signal that is advanced relative to the second clock signal by a phase corresponding to the determined skew, the advanced first clock signal generated based on the determined skew;
transmitting, by the memory controller, the advanced first clock signal to the first memory device and the second clock signal to the second memory device; and
simultaneously receiving third data from the first memory device and fourth data from the second memory device;
wherein the first memory device and the second memory device simultaneously read the third data and the fourth data from the first memory device and the second memory device, respectively, according to the advanced first clock signal and the second clock signal, respectively, and the reading of the third data and the fourth data is distinct from the first memory device and the second memory device simultaneously transmitting the third data and the fourth data to the memory controller.

2. The method of claim 1 , wherein the skew is determined as a number of unit intervals between the timings at which the first data and the second data are received at the memory controller.

3. The method of claim 1 , wherein generating the advanced first clock signal comprises generating additional edges in the first clock signal corresponding to the determined skew while pausing the first clock signal and the second clock signal.

4. The method of claim 1 , wherein generating the advanced first clock signal comprises gradually advancing the phase of the first clock signal relative to the second clock signal.

5. A memory controller for controlling a plurality of memory devices including at least a first memory device and a second memory device, the memory controller comprising:
a first interface circuit configured to forward a first clock signal to the first memory device and receive first data read from the first memory device according to the forwarded first clock signal via a first communication channel;
a second interface circuit configured to forward a second clock signal to the second memory device and receive second data read from the second memory device according to the forwarded second clock signal via a second communication channel; and
a controller circuit configured to cause the first interface circuit to generate an advanced first clock signal that is advanced relative to the second clock signal by a phase corresponding to a skew between timings when the first data and the second data are received by the first interface circuit and the second interface circuit, respectively;
wherein the first circuit interface is further configured to transmit the advanced first clock signal to the first memory device and wherein the second circuit interface is further configured to transmit the second clock signal to the second memory device;
wherein the first circuit interface and the second circuit interface are further configured to simultaneously receive third data from the first memory device and fourth data from the second memory device;
wherein the first memory device and the second memory device simultaneously read the third data and the fourth data from the first memory device and the second memory device, respectively, according to the advanced first clock signal and the second clock signal, respectively, and the reading of the third data and the fourth data is distinct from the first memory device and the second memory device simultaneously transmitting the third data and the fourth data to the first circuit interface and the second circuit interface of the memory controller.

6. The memory controller of claim 5 , wherein the controller circuit is configured to determine the skew between the first data and the second data.

7. The memory controller of claim 6 , wherein the skew is determined as a number of unit intervals between the timings at which the first data and the second data are received.

8. The memory controller of claim 5 , wherein the controller circuit is configured to cause the first interface circuit to generate the advanced first clock signal by generating additional edges in the first clock signal corresponding to the skew while pausing the first clock signal and the second clock signal.

9. The memory controller of claim 5 , wherein the controller circuit is configured to cause the first interface circuit to generate the advanced first clock signal by gradually advancing the phase of the first clock signal relative to the second clock signal.

10. In a memory controller for controlling a plurality of memory devices including at least a first memory device and a second memory device, a method comprising:
determining a skew between timings when first data and second data are received from the first memory device and the second memory device, respectively, the first data read from a first memory core of the first memory device according to a first clock signal forwarded from the memory controller via a first communication channel and the second data read from a second memory core from the second memory device according to a second clock signal forwarded from the memory controller via a second communication channel; and
transmitting a command to the first memory device, the command indicating to the first memory device that the first clock signal be advanced by the first memory device relative to the second clock signal by a phase corresponding to the determined skew;
wherein third data is read from the first memory core of the first memory device simultaneously with fourth data read from the second memory core of the second memory device according to the advanced first clock signal and the second clock signal respectively, and the third data and fourth data are simultaneously transmitted to the memory controller according to the advanced first clock signal and the second clock signal, respectively;
wherein the simultaneous reading of the third data and the fourth data from the first memory core of the first memory device and the second memory core of the second memory device is distinct from the simultaneous transmission of the third data and the fourth data to the memory controller.

11. The method of claim 10 , wherein the skew is determined as a number of unit intervals between the timings at which the first data and the second data are received at the memory controller.

12. The method of claim 10 , wherein the command is to generate additional edges in the first clock signal corresponding to the determined skew while pausing the first clock signal and the second clock signal.

13. The method of claim 10 , wherein the command is to gradually advance the phase of the first clock signal relative to the second clock signal.

14. A memory controller for controlling a plurality of memory devices including at least a first memory device and a second memory device, the memory controller comprising:
a first interface circuit configured to forward a first clock signal to the first me

Assignees

• Frans Yohan Usthavia
• Li Simon
• Rambus Inc

Inventors

• Frans Yohan Usthavia
• Li Simon

Classifications

• G06F13/1684

  using multiple buses · CPC title

• G06F13/1689 Primary

  Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title