Integrated system-in-package with radiation shielding

Patent metadata

Field	Value
Publication number	US-11978709-B2
Application number	US-202217752037-A
Country	US
Kind code	B2
Filing date	May 24, 2022
Priority date	Apr 16, 2020
Publication date	May 7, 2024
Grant date	May 7, 2024

Abstract

A system in a package (SIP) includes carrier layer regions that have a dielectric material with a metal post therethrough, where adjacent carrier layer regions define a gap. A driver IC die is positioned in the gap having nodes connected to bond pads exposed by openings in a top side of a first passivation layer, with the bond pads facing up. A dielectric layer is on the first passivation layer and carrier layer region that includes filled through vias coupled to the bond pads and to the metal post. A light blocking layer is on sidewalls and a bottom of the substrate. A first device includes a light emitter that has first bondable features. The light blocking layer can block at least 90% of incident light. The first bondable features are flipchip mounted to a first portion of the bond pads.

First claim

The invention claimed is:

1. A method of forming a system in a package (SIP), comprising:
providing carrier layer regions that comprises a dielectric material with at least one metal post through a thickness of the carrier layer region, adjacent ones of the carrier layer regions defining a gap having dimensions sufficient for placement of a driver integrated circuit (IC) die within the gap;
positioning the driver IC die within the gap, the driver IC die comprising a substrate having circuitry configured for a function with nodes connected to bond pads exposed by openings in a top side of a first passivation layer, wherein the driver IC die is positioned with the bond pads facing up;
forming a dielectric layer on the first passivation layer and on the carrier layer regions including filled vias therethrough coupled to the bond pads and to the metal post;
forming a light blocking layer on sidewalls and on a bottom side of the substrate; and
flipchip mounting a first device including a light emitter for emitting light at a wavelength having first bondable features to a first portion of the bond pads, wherein the flipchip mounting comprises forming a solder connection.

2. The method of claim 1 , wherein the light blocking layer has a thermal conductivity at 20° C. of at least 10 W/m·K and blocks at least 90% of the light that is incident thereon.

3. The method of claim 1 , further comprising flipchip mounting a second device having second bondable features positioned lateral to the first device to a second portion of the bond pads.

4. The method of claim 1 , further comprising forming a second passivation layer on the first passivation layer, and adding an additional light blocking passivation layer that comprises a buildup layer on a top side and on a bottom side of the SIP.

5. The method of claim 1 , further comprising dispensing a light blocking adhesive layer on the first passivation layer and forming a second passivation layer on the light blocking adhesive layer.

6. The method of claim 1 , further comprising forming a layer of backside metal on a back side of the driver IC die.

7. The method of claim 3 , wherein the second device comprises a resistor, capacitor, or an inductor.

8. The method of claim 1 , wherein the light emitter comprises a semiconductor laser or a light-emitting diode (LED), and wherein the wavelength is 500 nm to 2000 nm.

9. The method of claim 1 , wherein the light blocking layer comprises a metal, a metal alloy, or a polymer including carbon loading at a loading level of at least 1 weight %.

10. The method of claim 1 , further comprising forming the gap using laser drilling.

11. The method of claim 1 , further comprising forming metal pillars on the bond pads.

12. The method of claim 1 , wherein the light blocking layer has a thermal conductivity at 20° C. of at least 10 W/m·K.

13. A method of forming a system in a package (SIP), comprising:
providing carrier layer regions comprising a dielectric material with at least one metal post therethrough, adjacent ones of the carrier layer regions defining a gap having dimensions sufficient for placement of a driver integrated circuit (IC) die within the gap;
positioning the driver IC die within the gap, the driver IC die comprising a substrate having circuitry configured for a function with nodes connected to bond pads exposed by openings in a top side of a first passivation layer, wherein the driver IC die is positioned with the bond pads facing up;
forming a dielectric layer on the first passivation layer and on the carrier layer region including filled vias therethrough coupled to the bond pads and to the metal post;
forming a light blocking layer on sidewalls and on a bottom side of the substrate;
providing a first device including a light emitter for emitting light at a wavelength having first bondable features thereon; and
connecting the first bondable features to the bond pads.

14. The method of claim 13 , wherein the light blocking layer has a thermal conductivity at 20° C. of at least 10 W/m·K and blocks at least 90% of the light that is incident thereon.

15. The method of claim 13 ,
further comprising positioning a second device having second bondable features lateral to the first device,
wherein the second bondable features are connected to a second portion of the bond pads.

16. The method of claim 13 , further comprising forming a second passivation layer on the first passivation layer, and an additional light blocking passivation layer on the second passivation layer.

17. The method of claim 13 , further comprising forming a light blocking adhesive layer on the first passivation layer and a second passivation layer on the light blocking adhesive layer.

18. The method of claim 13 , further comprising forming a layer of backside metal on a back side of the driver IC die.

19. The method of claim 15 , wherein the second device comprises a resistor, capacitor, or an inductor.

20. The method of claim 13 , wherein the light emitter comprises a semiconductor laser or a light-emitting diode (LED), and wherein the wavelength is 500 nm to 2000 nm.

21. The method of claim 13 , wherein the light blocking layer comprises a metal, a metal alloy, or a polymer including carbon loading at a loading level of at least 1 weight %.

22. The method of claim 13 , wherein the dielectric layer includes carbon loading at a loading level of at least 1 weight % for light blocking.

23. A method of forming a system in a package (SIP), comprising:
providing a leadframe including a die pad and a plurality of leads or lead terminals, where the die pad and the leads or lead terminals are separated by a mold compound;
placing a driver integrated circuit (IC) die on the die pad comprising a substrate having circuitry configured for a function with nodes connected to a plurality of bond pads including a first bond pad, wherein the driver IC die is positioned on the die pad with the plurality of bond pads facing up;
placing a patterned redistribution layer (RDL) over a top side of the driver IC die;
forming a mold compound on sides of the driver IC die having metal posts throughout its thickness attached to the leads or the lead terminals;
wherein the RDL includes a first portion over the first bond pad, and traces between some of the plurality of bond pads and the metal posts;
attaching a first device including a light emitter for emitting light at a wavelength to first bondable features on the first portion of the RDL; and
wherein the RDL blocks at least 90% of the light that is incident thereon.

Assignees

• Texas Instruments Inc

Inventors

• Sridharan Vivek Swaminathan
• Tang Yiqi
• Manack Christopher Daniel
• Murugan Rajen Manicon
• Wan Liang
• Nguyen Hiep Xuan

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W70/099

  Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/874

  On different surfaces · CPC title