Leadframe-based system-in-packages having sidewall-mounted surface mount devices and methods for the production thereof

Patent metadata

Field	Value
Publication number	US-2016111403-A1
Application number	US-201514984092-A
Country	US
Kind code	A1
Filing date	Dec 30, 2015
Priority date	Mar 17, 2014
Publication date	Apr 21, 2016
Grant date	—

Abstract

Embodiments of a method for fabricating System-in-Packages (SiPs) are provided, as are embodiments of a SiP. In one embodiment, the method includes producing a first package including a first molded package body having a sidewall. A first leadframe is embedded within the first molded package body and having a first leadframe lead exposed through the sidewall. In certain implementations, a semiconductor die may also be encapsulated within the first molded package body. A Surface Mount Device (SMD) is mounted to the sidewall of the first molded package body such that a first terminal of the SMD is in ohmic contact with the first leadframe lead exposed through the sidewall.

First claim

What is claimed is:

1 . A System-In-Package (SiP), comprising:
a first package comprising:
a first molded package body having a sidewall; and
a first leadframe embedded within the first molded package body and having a first leadframe lead exposed through the sidewall; and
a Surface Mount Device (SMD) mounted to the sidewall of the first molded package body and having a first terminal ohmically contacting the first leadframe lead exposed through the sidewall of the first molded package body.

2 . The SiP of claim 1 wherein the SMD is selected from the group consisting of a capacitor, a diode, an inductor, and a resistor.

3 . The SiP of claim 1 wherein the first leadframe further comprises a leadframe lead exposed through the sidewall of the first molded package body, and wherein the SMD further has a second terminal ohmically contact the second lead frame lead exposed through the sidewall.

4 . The SiP of claim 3 wherein the SMD is mounted to the sidewall of the first molded package body in a horizontal orientation.

5 . SiP of claim 1 further comprising a second package bonded to the first package in stacked configuration, the second package comprising:
a second molded package body having a sidewall;
a second leadframe embedded within the second molded package body and having a second leadframe lead exposed through the sidewall;
wherein the SMD is further mounted to the sidewall of the second molded package body and has a second terminal ohmically contacting the second leadframe lead.

6 . The SiP of claim 5 wherein the SMD is mounted to the sidewalls of the first and second molded package bodies in a vertical orientation.

7 . The SiP claim 6 wherein the SMD comprises a passive microelectronic device having a first electrically-conductive end piece serving as the first terminal and having a second electrically-conductive end piece serving as a second terminal.

8 . A System-In-Package (SiP), comprising:
a first package comprising a first leadframe embedded within a first molded package body, the first leadframe having a first leadframe lead extending to a first sidewall of the first molded package body; a second package bonded to the first package in a stacked configuration, the second package comprising a second leadframe embedded within a second molded package body, the second leadframe having a second leadframe lead extending to a second sidewall of the second molded package body; and a Surface Mount Device (SMD) having first and second terminals, the SMD mounted to the first and second sidewalls such that the first terminal of the SMD electrically contacts the first leadframe lead and the second terminal of the SMD electrically contacts the second leadframe lead; wherein the SMD is selected from the group consisting of a discrete two terminal resistor providing a known resistance between the first and second leadframe leads, a discrete two terminal capacitor providing a known capacitance between the first and second leadframe leads, and a discrete two terminal inductor providing a known inductance between the first and second leadframe leads.

9 . The SiP of claim 8 wherein the SMD comprises a discrete two terminal resistor providing a resistance less than 0.1 ohms between the first and second leadframe leads.

10 . The SiP of claim 8 wherein the first and second terminals of the SMD are soldered to the first and second leadframe leads, respectively.

11 . The SiP of claim 8 wherein the first leadframe lead has an exposed face, which is substantially coplanar with the first sidewall of the first molded package body.

12 . The SiP of claim 8 wherein the SMD is mounted to the first and second sidewalls in a horizontal orientation.

13 . The SiP of claim 8 wherein the first package comprises:
a semiconductor die embedded in the first molded package body; and
one or more redistribution layers (RDLs) formed on the first molded package body, the RDLs containing at least one interconnect line electrically coupling the semiconductor die to the first leadframe lead.

14 . The SiP of claim 8 wherein the SMD is mounted to the first and second sidewalls in a vertical orientation.

15 . The SiP of claim 8 wherein the second package comprises one or more redistribution layers formed on the second molded package body, and wherein the first molded package body is bonded to the one or more redistribution layers.

16 . A System-In-Package (SiP), comprising:
a first molded package body having a sidewall; a semiconductor die embedded within the first molded package body; a Surface Mount Device (SMD) bonded to the sidewall of the first molded package body and having a first terminal; and a leadframe embedded within the first molded package body, the leadframe comprising:
a leadframe body; and
first and second leadframe leads extending from the leadframe body to the sidewall to electrically contact the first terminal of the SMD.

17 . The SiP of claim 16 wherein the SMD is selected from the group consisting of a discrete multiple terminal resistor, a discrete multiple terminal capacitor, and a discrete multiple terminal inductor.

18 . The SiP of claim 16 wherein the SMD is bonded to the sidewall of the first molded package body in a horizontal orientation.

19 . The SiP of claim 16 wherein the SMD is bonded to the sidewall of the first molded package body in a vertical orientation.

20 . The SiP of claim 16 further comprising:
a first package including the first molded package body, the semiconductor die, and the leadframe; and
a second package bonded to the first package in a stacked configuration and having a contact point;
wherein the SMD further includes a second terminal electrically coupled to the contact point of the second package.

Assignees

• Freescale Semiconductor Inc

Inventors

• Yap Weng F

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/801

  Interconnections on sidewalls of containers · CPC title

• H10W70/40

  Leadframes · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title