Semiconductor device stack-up with bulk substrate material to mitigate hot spots

Patent metadata

Field	Value
Publication number	US-11978689-B2
Application number	US-202218089537-A
Country	US
Kind code	B2
Filing date	Dec 27, 2022
Priority date	Jul 25, 2019
Publication date	May 7, 2024
Grant date	May 7, 2024

Abstract

Embodiments disclosed herein include semiconductor dies and methods of forming such dies. In an embodiment, the semiconductor die comprises a semiconductor substrate, an active device layer in the semiconductor substrate, where the active device layer comprises one or more transistors, an interconnect layer over a first surface of the active device layer, a first bonding layer over a surface of the semiconductor substrate, a second bonding layer secured to the first bonding layer, and a heat spreader attached to the second bonding layer.

First claim

What is claimed is:

1. A semiconductor die, comprising:
a substrate comprising silicon, the substrate having a top side opposite a bottom side;
an active device layer on the bottom side of the substrate;
interconnect layers below the active device layer, the interconnect layers comprising interlayer dielectric layers, conductive traces, and conductive vias;
a first bonding layer on the top side of the substrate, the first bonding layer comprising silicon and oxygen;
a second bonding layer on the first bonding layer, the second bonding layer comprising silicon and oxygen;
a heat spreader on the second bonding layer, the heat spreader comprising silicon.

2. The semiconductor die of claim 1 , wherein the first bonding layer and the second bonding layer have a combined thickness of approximately 3 microns or less.

3. The semiconductor die of claim 1 , wherein the substrate has a thickness less than approximately 10 microns.

4. The semiconductor die of claim 1 , wherein the first bonding layer is in direct contact with the second bonding layer.

5. The semiconductor die of claim 1 , further comprising:
a seam between the first bonding layer and the second bonding layer.

6. The semiconductor die of claim 1 , wherein the heat spreader has a thermal conductivity greater than a thermal conductivity of the substrate.

7. The semiconductor die of claim 1 , further comprising:
a second heat spreader coupled to the first heat spreader.

8. The semiconductor die of claim 1 , further comprising:
a thermal interface material between the heat spreader and the second heat spreader.

9. A semiconductor die, comprising:
a substrate comprising silicon, the substrate having a top side opposite a bottom side;
an active device layer on the bottom side of the substrate;
an interconnect layer below the active device layer, the interconnect layer comprising a plurality of alternating interlayer dielectric layers and layers of conductive traces, and a plurality of conductive vias coupling the layers of conductive traces;
a structure comprising silicon, the structure over the substrate;
a bonding layer between the structure and the substrate; and
a heat spreader on the structure.

10. The semiconductor die of claim 9 , wherein the bonding layer comprises a first bonding layer and a second bonding layer.

11. The semiconductor die of claim 10 , wherein the first bonding layer comprises silicon and oxygen.

12. The semiconductor die of claim 10 , wherein the first and second bonding layers comprise silicon and oxygen.

13. The semiconductor die of claim 10 , wherein the first bonding layer comprises silicon and oxygen, and the second bonding layer comprises silicon and nitrogen.

14. The semiconductor die of claim 9 , wherein the bonding layer comprises a layer comprising silicon and nitrogen.

15. The semiconductor die of claim 9 , wherein the bonding layer has a thickness of approximately 3 microns or less, and wherein the substrate has a thickness less than approximately 10 microns.

16. A method of fabricating a semiconductor die, the method comprising:
providing a substrate comprising silicon, the substrate having a top side opposite a bottom side;
forming an active device layer on the bottom side of the substrate;
forming interconnect layers below the active device layer, the interconnect layers comprising interlayer dielectric layers, conductive traces, and conductive vias;
forming a first bonding layer on the top side of the substrate, the first bonding layer comprising silicon and oxygen;
forming a second bonding layer on the first bonding layer, the second bonding layer comprising silicon and oxygen;
forming a heat spreader on the second bonding layer, the heat spreader comprising silicon.

17. The method of claim 16 , wherein the first bonding layer and the second bonding layer have a combined thickness of approximately 3 microns or less, and wherein the substrate has a thickness less than approximately 10 microns.

18. The method of claim 16 , wherein the first bonding layer is in direct contact with the second bonding layer.

19. The method of claim 16 , wherein a seam is between the first bonding layer and the second bonding layer.

20. The method of claim 16 , further comprising:
forming a second heat spreader coupled to the first heat spreader.

Assignees

• Intel Corp

Inventors

• Kothari Shrenik
• JHA Chandra Mohan
• Tang Weihua
• Sankman Robert
• Brun Xavier
• Tadayon Pooya

Classifications

• H10W90/811

  Multiple chips on leadframes · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W70/68

  Shapes or dispositions thereof · CPC title