Semiconductor package with low parasitic connection to passive device

Patent metadata

Field	Value
Publication number	US-11973063-B2
Application number	US-202117379529-A
Country	US
Kind code	B2
Filing date	Jul 19, 2021
Priority date	Jul 19, 2021
Publication date	Apr 30, 2024
Grant date	Apr 30, 2024

Abstract

A semiconductor assembly includes a semiconductor package that includes first and second transistor dies embedded within a package body, the first and second transistor dies being arranged laterally side by side within the package body such that a first load terminal of the first transistor die faces an upper surface of the package body and such that a second load terminal of the second transistor die faces the upper surface of the package body, and a discrete capacitor mounted on the semiconductor package such that a first terminal of the discrete capacitor is directly over and electrically connected to the first load terminal of the first semiconductor die and such that a second terminal of the discrete capacitor is directly over and electrically connected with the second load terminal of the second semiconductor die.

First claim

The invention claimed is:

1. A semiconductor assembly, comprising:
a semiconductor package that comprises first and second transistor dies embedded within a package body, the first and second transistor dies being arranged laterally side by side within the package body such that a first load terminal of the first transistor die faces an upper surface of the package body and such that a second load terminal of the second transistor die faces the upper surface of the package body, and
a discrete capacitor mounted on the semiconductor package such that a first terminal of the discrete capacitor is directly over and electrically connected to the first load terminal of the first semiconductor die and such that a second terminal of the discrete capacitor is directly over and electrically connected with the second load terminal of the second semiconductor die.

2. The semiconductor assembly of claim 1 , wherein the first and second transistor dies are each vertical devices, and wherein a vertical orientation of the first power transistor die is opposite to the second power transistor die.

3. The semiconductor assembly of claim 2 , wherein the semiconductor package further comprises a first structured metallization layer disposed on the upper surface of the package body, wherein the first structured metallization layer comprises a first bond pad that is directly over and electrically connected to the first load terminal of the first semiconductor die, and a second bond pad that is directly over and electrically connected to the second load terminal of the second semiconductor die.

4. The semiconductor assembly of claim 3 , wherein the first terminal of the discrete capacitor is adhesively conductively connected to the first bond pad, and wherein the second terminal of the discrete capacitor is adhesively conductively connected to the second bond pad.

5. The semiconductor assembly of claim 3 , wherein the semiconductor package further comprises a second structured metallization layer disposed on a lower surface of the package body that is opposite the upper surface of the package body, wherein the second structured metallization layer comprises:
a third bond pad that is electrically connected to the first bond pad by a first through-via; and
a fourth bond pad that is electrically connected to the second bond pad by a second through-via, and
wherein both of the first and second transistor dies are laterally between the first and second through-vias.

6. The semiconductor assembly of claim 2 , further comprising:
a carrier comprising an electrically insulating substrate; and
a plurality of the semiconductor packages mounted on the carrier,
wherein the first bond pads from each of the semiconductor packages in the plurality are electrically connected to one another by a first metal interconnect structure, and
wherein the second bond pads from each of the semiconductor packages in the plurality are electrically connected to one another by a second metal interconnect structure.

7. The semiconductor assembly of claim 6 , wherein one or both of the first and second metal interconnect structures are metal bars that are disposed completely above the plurality of the semiconductor packages.

8. The semiconductor assembly of claim 6 , wherein one or both of the first and second metal interconnect structures are metal clips that are connected between the semiconductor packages and the carrier.

9. A semiconductor assembly, comprising:
a semiconductor package that comprises a power converter circuit monolithically integrated into a package body, the power converter circuit comprising a first load terminal and a second load terminal, the first and second load terminals each facing an upper surface of the package body; and
a discrete capacitor mounted on the semiconductor package such that a first terminal of the discrete capacitor is directly over and electrically connected to the first load terminal and such that a second terminal of the discrete capacitor is directly over and electrically connected with second load terminal.

10. The semiconductor assembly of claim 9 , wherein the power converter circuit comprises first and second transistor dies embedded within the package body, wherein the first and second transistor dies are each configured as a discrete power MOSFET, wherein the first load terminal corresponds to a drain terminal of the first transistor die, and wherein the second load terminal corresponds to a source terminal of the second transistor die.

11. The semiconductor assembly of claim 10 , wherein the power converter circuit is configured as a half-bridge circuit, wherein the first transistor die is a high-side switch of the half-bridge circuit, and wherein the second transistor die is a low-side switch of the half-bridge circuit.

12. The semiconductor assembly of claim 9 , wherein the first terminal of the discrete capacitor is a metal contact or lead that is adhesively conductively attached to the first load terminal, and wherein the second terminal of the discrete capacitor is a metal contact or lead that is adhesively conductively attached to the second load terminal.

Assignees

• Infineon Technologies Ag

Inventors

• Medic Urban
• Cho Eung San
• Naeve Tomasz

Classifications

• H10W90/763

  between laterally-adjacent chips · CPC title

• H10W72/07236

  Soldering or alloying · CPC title

• H10W72/90

  Bond pads, in general · CPC title

• H10W72/076

  of strap connectors · CPC title

• H10W70/635

  Through-vias · CPC title