Bootstrap capacitor over-voltage management circuit for GaN transistor based power converters

Patent metadata

Field	Value
Publication number	US-10454472-B2
Application number	US-201715824275-A
Country	US
Kind code	B2
Filing date	Nov 28, 2017
Priority date	Dec 1, 2016
Publication date	Oct 22, 2019
Grant date	Oct 22, 2019

Abstract

A drive circuit for a half bridge transistor circuit formed of enhancement mode GaN transistors. A shunt diode is connected to the bootstrap capacitor at a node between the bootstrap capacitor and ground, the shunt diode being decoupled from the midpoint node of the half bridge by a shunt resistor. The shunt diode advantageously provides a low voltage drop path to charge the bootstrap capacitor during the dead-time charging period when both the high side and low side transistors of the half bridge are off.

First claim

What is claimed is:

1. An electrical circuit arranged in a half bridge topology, comprising:
a high side transistor and a low side transistor, each having a source, a drain and a gate, the source of the high side transistor being electrically connected to the drain of the low side transistor at a first node;
a gate driver electrically coupled to the gate of the high side transistor;
a bootstrap capacitor electrically coupled in parallel with the gate driver;
a shunt diode having a cathode and an anode, the cathode of the shunt diode being connected to the capacitor at a second node, and the anode of the shunt diode being connected to ground, the shunt diode providing a low voltage drop path to charge the bootstrap capacitor; and
a shunt resistor electrically connected between the first node and the second node, to decouple the shunt diode from the first node, and to control and limit current through the shunt diode.

2. The electrical circuit of claim 1 , wherein the high side and low side transistors are enhancement mode GaN transistors.

3. The electrical circuit of claim 1 , further comprising a turn on diode electrically connected in anti-parallel with the shunt resistor.

4. The electrical circuit of claim 3 , further comprising a turn on resistor in series with the turn on diode.

5. The electrical circuit of claim 3 , further comprising a second shunt diode, the second shunt diode connected in series with the shunt resistor.

6. The electrical circuit of claim 1 , further comprising additional shunt diodes and shunt resistors connected to respective sources of additional high side transistors.

7. The electrical circuit of claim 1 , wherein the shunt diode is substituted with a shunt transistor, the shunt transistor being driven with a gate drive signal that is complementary to the signal applied to the gate of the low side transistor.

8. The electrical circuit of claim 1 , wherein the gate driver, the bootstrap capacitor, the shunt diode and the shunt resistor are all fully integrated monolithically into a single integrated circuit.

9. The electrical circuit of claim 1 , wherein the integrated circuit includes the high side and low side transistors and passive components of the circuit.

10. A method of avoiding gate drive overvoltage in an electrical circuit arranged in a half bridge configuration, wherein the half bridge of the electrical circuit comprises a high side transistor and a low side transistor, each having a source, a drain and a gate, the source of the high side transistor being electrically connected to the drain of the low side transistor at a first node, and the electrical circuit further comprises a gate driver electrically coupled to the gate of the high side transistor, and a bootstrap capacitor electrically coupled in parallel with the gate driver, wherein the method comprises charging the bootstrap capacitor, when both the high side and low side transistors are off, through a shunt network electrically connected in parallel to the low side transistor, the shunt network providing a low voltage drop charging path as compared to the reverse voltage drop of the low side transistor, wherein the shunt network comprises:
a shunt diode having a cathode and an anode, the cathode of the shunt diode being connected to the capacitor at a second node, and the anode of the shunt diode being connected to ground, and
a shunt resistor electrically connected between the first node and the second node to decouple the shunt diode from the first node, and to control and limit current through the shunt diode.

11. The method of claim 10 , wherein the high side and low side transistors are enhancement mode GaN transistors.

12. The method of claim 10 , wherein the shunt network further comprises a turn on diode electrically connected in anti-parallel with respect to the shunt resistor.

13. The method of claim 10 , wherein the shunt network further comprises a turn on resistor in series with the turn on diode.

14. The method of claim 13 , further comprising a second shunt diode, the second shunt diode being disposed in series with the shunt resistor.

15. The method of claim 10 , wherein the shunt diode is substituted with a shunt transistor, and the shunt transistor is driven with a gate drive signal that is complementary to the signal applied to the gate of the low side transistor.

Assignees

• Efficient Power Conversion Corp

Inventors

• Reusch David C
• Glaser John
• De Rooij Michael A

Classifications

• H03K17/04206

  in field-effect transistor switches · CPC title

• H02M3/158

  including plural semiconductor devices as final control devices for a single load · CPC title

• H03K2217/0063

  High side switches, i.e. the higher potential [DC] or life wire [AC] being directly connected to the switch and not via the load · CPC title

• H03K17/567 Primary

  Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT · CPC title

• H03K2217/0072

  Low side switches, i.e. the lower potential [DC] or neutral wire [AC] being directly connected to the switch and not via the load · CPC title