Nanotwin copper materials in semiconductor devices

Patent metadata

Field	Value
Publication number	US-11973034-B2
Application number	US-202117411321-A
Country	US
Kind code	B2
Filing date	Aug 25, 2021
Priority date	Aug 25, 2021
Publication date	Apr 30, 2024
Grant date	Apr 30, 2024

Abstract

Exemplary methods of electroplating a metal with a nanotwin crystal structure are described. The methods may include plating a metal material into at least one opening on a patterned substrate, where at least a portion of the metal material is characterized by a nanotwin crystal structure. The methods may further include polishing an exposed surface of the metal material in the opening to reduce an average surface roughness of the exposed surface to less than or about 1 nm. The polished exposed surface may include at least a portion of the metal material characterized by the nanotwin crystal structure. In additional examples, the nanotwin-phased metal may be nanotwin-phased copper.

First claim

What is claimed is:

1. An electroplating method comprising:
plating a metal material into at least one opening on a patterned substrate, wherein at least a portion of the metal material is characterized by a nanotwin crystal structure; and
polishing an exposed surface of the metal material in the opening to reduce an average surface roughness of the exposed surface to less than or about 1 nm, wherein the polished exposed surface comprises at least a portion of the metal material characterized by the nanotwin crystal structure.

2. The electroplating method of claim 1 , wherein the metal material characterized by the nanotwin crystal structure is nanotwin copper.

3. The electroplating method of claim 2 , wherein the metal material comprises at least a second metal selected from the group consisting of silver, gold, and platinum.

4. The electroplating method of claim 1 , wherein the exposed surface of the metal material is polished with chemical mechanical polishing.

5. The electroplating method of claim 1 , wherein the exposed surface of the metal material is further polished with electropolishing.

6. The electroplating method of claim 1 , wherein the polishing of the exposed surface of the metal material is performed in an oxygen-free environment, and wherein the polishing removes one or more metal oxides from the exposed surface of the metal material.

7. The electroplating method of claim 1 , wherein the metal material comprises a first portion in contact with a bottom surface of the opening that is free of the nanotwin crystal structure and a second portion in contact with the polished exposed surface that comprises the nanotwin crystal structure.

8. The electroplating method of claim 7 , wherein the patterned substrate further comprises a barrier layer positioned between the first portion and the second portion of the metal material in the opening.

9. An electroplating method comprising:
plating a first portion of a metal material on a bottom portion of at least one opening on a patterned substrate, wherein the first portion of the metal material is substantially free of nanotwin crystal structures;
forming a barrier layer on the first portion of the metal material;
plating a second portion of the metal material on the barrier layer, wherein the second portion of the metal material is characterized by a nanotwin crystal structure; and
polishing an exposed surface of the second portion of the metal material in the opening to reduce an average surface roughness of the exposed surface to less than or about 1 nm.

10. The electroplating method of claim 9 , wherein the first portion of the metal material is greater than or about 50 wt. % of a total amount of the metal material in the opening.

11. The electroplating method of claim 9 , wherein the metal material is copper.

12. The electroplating method of claim 11 , wherein the second portion of the metal material comprises at least a second metal selected from the group consisting of silver, gold, and platinum.

13. The electroplating method of claim 9 , wherein the barrier layer comprises a metal that is not included in the second portion of the metal material.

14. An integrated circuit device structure comprising:
a patterned substrate comprising at least one opening, wherein the opening includes a top portion and bottom surface; and
a metal-containing material filling at least the top portion of the opening, wherein the metal-containing material comprises an exposed surface having an average surface roughness of the exposed surface to less than or about 1 nm, and wherein the metal-containing material is characterized by a nanotwin crystal structure.

15. The integrated circuit device structure of claim 14 , wherein the patterned substrate further comprises a barrier layer positioned between the metal-containing material filling the top portion of the opening and a second portion of the metal-containing material in contact with the bottom surface of the opening.

16. The integrated circuit device structure of claim 15 , wherein the second portion of the metal-containing material is free of the nanotwin crystal structure.

17. The integrated circuit device structure of claim 14 , wherein the metal-containing material comprises copper.

18. The integrated circuit device structure of claim 17 , wherein the metal-containing material in the top portion of the opening comprises at least a second metal selected from the group consisting of silver, gold, and platinum.

19. The integrated circuit device structure of claim 14 , wherein the opening is characterized by an aspect ratio greater than or about 1:1.

Assignees

• Applied Materials Inc

Inventors

• Bergman Eric J
• Klocke John L
• Bernt Marvin L
• Xu Jing
• Roh Kwan Wook

Classifications

• H10P14/47 Primary

  Electrolytic deposition, i.e. electroplating; Electroless plating · CPC title

• H10W20/062

  by smoothing of conductive parts, e.g. by planarisation · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title