Capacitor, connection structure, and method for manufacturing capacitor

Patent metadata

Field	Value
Publication number	US-11972909-B2
Application number	US-202217666961-A
Country	US
Kind code	B2
Filing date	Feb 8, 2022
Priority date	Aug 27, 2019
Publication date	Apr 30, 2024
Grant date	Apr 30, 2024

Abstract

A capacitor disposed inside a multilayer substrate that includes a conductive pattern on a surface thereof and an anode portion having a first conductive metal member and a porous portion disposed on a surface of the first conductive metal member, a cathode portion, and a dielectric layer disposed between the anode portion and the cathode portion. Moreover, the anode portion is led out to a surface side of the multilayer substrate by a connection electrode including an alloy layer containing a metal forming the first conductive metal member and a conductive layer disposed on the alloy layer, and in which the connection electrode is connected to the conductive pattern formed on the surface of the multilayer substrate.

First claim

The invention claimed is:

1. A capacitor disposed inside a multilayer substrate having a conductive pattern on a surface thereof, the capacitor comprising:
an anode portion including a first conductive metal member and a porous portion arranged on a surface of the first conductive metal member;
a cathode portion; and
a dielectric layer disposed between the anode portion and the cathode portion,
wherein the anode portion is led out to the surface of the multilayer substrate by a connection electrode including an alloy layer containing a metal forming the first conductive metal member and a conductive layer disposed on the alloy layer, and
wherein the connection electrode is connected to the conductive pattern disposed on the surface of the multilayer substrate.

2. The capacitor according to claim 1 , wherein the connection electrode sandwiches the anode portion from above and below in a thickness direction of the multilayer substrate.

3. The capacitor according to claim 1 , wherein the connection electrode includes the alloy layer and a plating layer constructed as the conductive layer.

4. The capacitor according to claim 3 , wherein an irregularity is disposed on a surface of the alloy layer, and the plating layer extends into the irregularity.

5. The capacitor according to claim 1 , wherein the alloy layer includes an alloy of aluminum and copper or nickel.

6. The capacitor according to claim 1 , wherein the first conductive metal member contains aluminum, and the capacitor is an aluminum solid electrolytic capacitor.

7. The capacitor according to claim 1 , wherein at least one of a load and a voltage regulator is electrically connected to the conductive pattern disposed on the surface of the multilayer substrate.

8. The capacitor according to claim 1 , wherein a through-hole extends in a thickness direction of the multilayer substrate and is connected to the cathode portion and an additional conductive pattern disposed on the surface of the multilayer substrate.

9. The capacitor according to claim 8 , further comprising a first resin insulating layer disposed on the anode portion, a second resin insulating layer disposed on the first resin insulating layer, and a surface-layer resin insulating layer disposed on the second resin insulating layers to form the surface of the multilayer substrate.

10. The capacitor according to claim 9 , wherein the cathode portion includes a solid electrolyte layer disposed on the porous portion of the anode portion, a conductive layer disposed on the solid electrolyte layer and a cathode lead-out layer extending from the conductive layer and on the first resin insulating layer to the through-hole.

11. A capacitor disposed in a multilayer substrate having at least one conductive pattern disposed on a surface thereof, the capacitor comprising:
an anode having a first conductive metal member with a porous surface;
a cathode having a plurality of layers disposed on opposing sides of the anode;
a dielectric layer disposed between the anode and the cathode; and
a connection electrode that couples the anode to the surface of the multilayer substrate, with the connection electrode including an alloy layer containing a metal of the first conductive metal member and a conductive layer disposed on the alloy layer, and
wherein the connection electrode is connected to the at least one conductive pattern on the surface of the multilayer substrate.

12. The capacitor according to claim 11 , wherein the connection electrode sandwiches the anode from above and below in a thickness direction of the multilayer substrate.

13. The capacitor according to claim 11 ,
wherein the connection electrode includes the alloy layer and a plating layer constructed as the conductive layer, and
wherein an irregularity is disposed on a surface of the alloy layer, and the plating layer extends into the irregularity.

14. The capacitor according to claim 11 , wherein the first conductive metal member contains aluminum, and the capacitor is an aluminum solid electrolytic capacitor.

15. The capacitor according to claim 11 , wherein at least one of a load and a voltage regulator is electrically connected to the at least one conductive pattern on the surface of the multilayer substrate.

16. The capacitor according to claim 11 , wherein a through-hole extends in a thickness direction of the multilayer substrate and is connected to the cathode and the at least one conductive pattern disposed on the surface of the multilayer substrate.

17. The capacitor according to claim 16 , further comprising a first resin insulating layer disposed on the anode, a second resin insulating layer disposed on the first resin insulating layer, and a surface-layer resin insulating layer disposed on the second resin insulating layers to form the surface of the multilayer substrate.

18. The capacitor according to claim 17 , wherein the plurality of layers of the cathode include a solid electrolyte layer disposed on the porous surface of the anode, a conductive layer disposed on the solid electrolyte layer and a cathode lead-out layer extending from the conductive layer and on the first resin insulating layer to the through-hole.

19. A method for manufacturing a capacitor disposed in a multilayer substrate, the method comprising:
providing a metal layer on a surface of a first conductive metal member with the metal layer being a metal different from a metal forming the first conductive metal member;
irradiating the metal layer with laser light to form an alloy layer containing the metal forming the first conductive metal member and the metal contained in the metal layer by; and
forming a connection electrode by providing a conductive layer on the alloy layer to lead out the connection electrode to a surface of the multilayer substrate.

20. The method for manufacturing the capacitor according to claim 19 , further comprising forming a plating layer as the conductive layer by plating the alloy layer.

Assignees

• Murata Manufacturing Co

Inventors

• Nakamura Kazutaka
• Shimada Kohei
• Furukawa Takeshi
• Otani Shinji
• Takahashi Akitomo

Classifications

• H01G9/042 Primary

  characterised by the material (H01G11/22 takes precedence) · CPC title

• H01G9/0029

  Processes of manufacture · CPC title

• H01G9/15 Primary

  Solid electrolytic capacitors (H01G11/00 takes precedence) · CPC title

• H05K1/182

  associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC] · CPC title

• H05K2201/10015

  Non-printed capacitor · CPC title