Interconnections for modular die designs

Patent metadata

Field	Value
Publication number	US-11972189-B2
Application number	US-202217655823-A
Country	US
Kind code	B2
Filing date	Mar 22, 2022
Priority date	Mar 22, 2022
Publication date	Apr 30, 2024
Grant date	Apr 30, 2024

Abstract

Interconnections for modular die designs are disclosed. In one aspect, a die that is a chiplet is designed and tested for suitability. After approval of the chiplet design, multiple dies or chiplets may be coupled together within a multi-die package to form a package having desired computing capabilities. After assembly, each chiplet is provided a unique identifier, such as by setting a fuse. Based on the unique identifier, each chiplet is made aware of how interfaces to other chiplets are configured so that signals may be routed appropriately. Using modular chiplets in this fashion reduces testing requirements and non-recurring expenses while increasing flexibility for design options.

First claim

What is claimed is:

1. A method of forming a package, the method comprising:
placing a plurality of chiplets on a substrate;
setting a unique identifier for each chiplet by setting at least one fuse;
forming a look-up table (LUT) for each chiplet for routing communication between chiplets based on the unique identifiers; and
based on the unique identifiers, configuring ports to route communication between chiplets.

2. The method of claim 1 , wherein the plurality of chiplets are homogeneous.

3. The method of claim 1 , wherein the plurality of chiplets are heterogeneous.

4. The method of claim 1 , wherein setting the unique identifier comprises grounding a circuit.

5. The method of claim 1 , wherein setting the unique identifier comprises setting the unique identifier using software.

6. The method of claim 1 , wherein placing the plurality of chiplets on the substrate comprises forming interconnections therebetween using vias and conductors within metallization layers within the substrate.

7. The method of claim 1 , further comprising assigning each chiplet the unique identifier prior to setting.

8. The method of claim 1 , further comprising loading the look-up table (LUT) with global versus local address information based on the unique identifiers.

9. The method of claim 1 , wherein placing the plurality of chiplets on the substrate comprises coupling a first port of a first chiplet to a first port of a second chiplet.

10. A method of communication between chiplets in a package, the method comprising:
generating a signal at a logical block within a first chiplet in the package;
comparing an address for the signal to a look-up table (LUT) to determine a physical address, wherein each chiplet of the chiplets has a unique identifier defined by at least one fuse and wherein the LUT contains routing communication between the chiplets based on the unique identifiers; and
sending the signal to a selected port based on the LUT.

11. A package comprising:
a substrate; and
a plurality of chiplets mounted on the substrate and interconnected to one another;
each chiplet of the plurality of chiplets comprising:
a unique identifier;
a plurality of ports;
a look-up table (LUT); and
a control circuit configured to discriminate whether signals generated within the chiplet are local or directed to a different chiplet based on the LUT.

12. The package of claim 11 , wherein the plurality of chiplets are homogeneous.

13. The package of claim 11 , wherein the plurality of chiplets are heterogeneous.

14. The package of claim 11 , wherein the substrate comprises metallization layers including conductors and vias, and the plurality of chiplets are interconnected using the conductors and the vias.

15. A package comprising:
a substrate; and
a plurality of chiplets mounted on the substrate and interconnected to one another;
each chiplet of the plurality of chiplets comprising:
a unique identifier;
a plurality of ports; and
a control circuit configured to route signals generated within the chiplet to a local address or to a different chiplet within the plurality of chiplets based on a chiplet identifier within a signal.

16. The package of claim 15 , wherein the chiplet identifier is prepended to an address within the signal.

17. The package of claim 15 , wherein the chiplet identifier comprises a number of bits equal to one plus a number of bits required to identify uniquely the plurality of chiplets.

18. A package comprising:
a substrate; and
a plurality of chiplets mounted on the substrate and interconnected to one another;
each chiplet of the plurality of chiplets comprising:
a unique identifier;
a plurality of ports; and
a control circuit configured to route signals generated within the chiplet to a local address or to an outgoing port based on a chiplet identifier.

Assignees

• Qualcomm Inc

Inventors

• Kamdar Siddharth
• Avoinne Christophe
• Arya Sanjay Jaisingh
• Shah Manav

Classifications

• G06F2113/18

  Chip packaging · CPC title

• G11C8/12

  Group selection circuits, e.g. for memory block selection, chip selection, array selection · CPC title

• G11C5/06

  Arrangements for interconnecting storage elements electrically, e.g. by wiring · CPC title

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/394 Primary

  Routing (G06F30/396 takes precedence) · CPC title