Hardware and software hybrid configuration of DRAM channel interleaving management
US-12596641-B2 · Apr 7, 2026 · US
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Avoinne Christophe patents
Avoinne Christophe is listed as an inventor on 19 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Avoinne Christophe |
| Total patents | 19 |
| First publication | Dec 8, 2016 |
| Latest publication | Apr 7, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Memory tagging in a computing system
US-2025348431-A1 · Nov 13, 2025 · US
Slice-based memory channel power control
US-2025348235-A1 · Nov 13, 2025 · US
Communicating data and command messages and point-to-point signaling using a multi-bit line network-on-chip
US-2025323878-A1 · Oct 16, 2025 · US
Hardware And Software Hybrid Configuration Of DRAM Channel Interleaving Management
US-2025245141-A1 · Jul 31, 2025 · US
Systems and methods of exchanging data using a communication link
US-2025226854-A1 · Jul 10, 2025 · US
Communication of thermal states for chiplets
US-2025189385-A1 · Jun 12, 2025 · US
Interconnections for modular die designs
US-11972189-B2 · Apr 30, 2024 · US
Package comprising integrated devices
US-2024038672-A1 · Feb 1, 2024 · US
Interconnections for modular die designs
US-2023325576-A1 · Oct 12, 2023 · US
Recent patents
Latest publications not already listed above.
System for providing a low latency and fast switched cascaded dual phased lock loop (PLL) architecture for die-to-die / system-on-chip (SoC) interfaces
US-11662765-B1 · May 30, 2023 · US
Dram-aware caching
US-11520706-B2 · Dec 6, 2022 · US
Dram-aware caching
US-2022350749-A1 · Nov 3, 2022 · US
Coherent interconnect power reduction using hardware controlled split snoop directories
US-10606339-B2 · Mar 31, 2020 · US
Mechanisms to enforce security with partial access control hardware offline
US-2019012271-A1 · Jan 10, 2019 · US
Coherent Interconnect Power Reduction Using Hardware Controlled Split Snoop Directories
US-2018067542-A1 · Mar 8, 2018 · US
Interconnect distributed virtual memory (DVM) message preemptive responding
US-9910799-B2 · Mar 6, 2018 · US
Interconnect Distributed Virtual Memory Message Preemptive Responding
US-2017286335-A1 · Oct 5, 2017 · US
Memory interleaving on memory channels
US-2016357666-A1 · Dec 8, 2016 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Qualcomm Inc | 17 |
| Texas Instruments Inc | 1 |
| Qualcomm Incorporated | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| Y02D10/00 | 9 |
| G06F12/0893 | 4 |
| G06F12/0607 | 4 |
| G06F2212/1024 | 3 |
| G06F2212/1028 | 3 |