Sputtering target including carbon-doped GST and method for fabricating electronic device using the same

Patent metadata

Field	Value
Publication number	US-11968912-B2
Application number	US-202117324833-A
Country	US
Kind code	B2
Filing date	May 19, 2021
Priority date	Dec 16, 2020
Publication date	Apr 23, 2024
Grant date	Apr 23, 2024

Abstract

A sputtering target and a method for fabricating an electronic device using the same are provided. A sputtering target may include a carbon-doped GeSbTe alloy, wherein, for the carbon-doped GeSbTe alloy, an average grain diameter of a GeSbTe alloy after sintering is in a range of 0.5 μm to 5 μm, and a first ratio of an average grain diameter of carbon after the sintering is Y (μm) to the average grain diameter of the GeSbTe alloy after the sintering may be in a range of greater than 0.5 and equal to or less than 1.5. Alternatively, for the carbon-doped GeSbTe alloy, a condition of Y=X×(Z/100) may be satisfied, where an average grain diameter of a GeSbTe alloy after sintering is X (μm), an average grain diameter of carbon after the sintering is Y (μm), and a content of carbon is Z (at %).

First claim

What is claimed is:

1. A method for fabricating an electronic device including a semiconductor memory, the method comprising:
forming a plurality of first lines over a substrate, each first line extending in a first direction;
forming a plurality of memory cells over the first lines; and
forming a plurality of second lines over the memory cells, each second line extending in a second direction that crosses the first direction, the first and second directions being perpendicular to a top surface of the substrate,
wherein forming the plurality of memory cells comprises:
forming a plurality of lower electrode layers over the first lines;
forming a plurality of selection element layers over the plurality of lower electrode layers;
forming a plurality of middle electrode layers over the plurality of selection element layers;
forming a plurality of variable resistance layers over the plurality of middle electrode layers; and
forming a plurality of upper electrode layers over the plurality of variable resistance layers,

wherein the memory cells are disposed at respective intersections of the plurality of first lines and the plurality of second lines,
wherein the lower electrode layers are configured to carry a voltage or a current between a corresponding one of the first lines and said each of the memory cells,
wherein the selection element layers are configured to control accessing to the variable resistance layers,
wherein the middle electrode layers are configured to physically separate the selection element layers from the variable resistance layers and to electrically couple the selection element layers to the variable resistance layers,
wherein the variable resistance layers are configured to switch between different resistance states according to an applied voltage or current,
wherein each of the upper electrode layers is configured to provide a transmission path of a voltage or a current between said each of the variable resistance layers and a corresponding one of the second lines,
wherein the variable resistance layers are formed by a sputtering process using a sputtering target, the sputtering target including a carbon-doped GeSbTe alloy, and
wherein an average grain diameter of a GeSbTe alloy after sintering is in a range of 0.5 μm to 5 μm, and a first ratio of an average grain diameter of carbon after the sintering to the average grain diameter of the GeSbTe alloy after the sintering is in a range of greater than 0.5 and equal to or less than 1.5.

2. The method of claim 1 , wherein the selection element layer has a single-layered structure, or a multi-layered structure that exhibits a selection element characteristic using a combination of two or more layers.

3. The method of claim 1 , wherein the first ratio is in a range of 0.8 to 1.2.

4. The method of claim 1 , wherein the carbon-doped GeSbTe alloy is formed using 5 to 25 at % of germanium, 20 to 40 at % of antimony, 40 to 60 at % of tellurium, and 0.1 to 20 at % of carbon.

5. The method of claim 1 , wherein a second ratio of an average powder diameter of carbon before the sintering to an average powder diameter of the GeSbTe alloy before the sintering is in a range of greater than 0.5 and equal to or less than 1.5.

6. The method of claim 5 , wherein the second ratio is in a range of 0.8 to 1.2.

7. A method for fabricating an electronic device including a semiconductor memory, the method comprising:
forming a plurality of first lines over a substrate, each first line extending in a first direction;
forming a plurality of memory cells over the first lines; and
forming a plurality of second lines over the memory cells, each second line extending in a second direction that crosses the first direction, the first and second directions being perpendicular to a top surface of the substrate,
wherein forming the plurality of memory cells comprises:
forming a plurality of lower electrode layers over the first lines;
forming a plurality of selection element layers over the plurality of lower electrode layers;
forming a plurality of middle electrode layers over the plurality of selection element layers;
forming a plurality of variable resistance layers over the plurality of middle electrode layers; and
forming a plurality of upper electrode layers over the plurality of variable resistance layers,

wherein the memory cells are disposed at respective intersections of the plurality of first lines and the plurality of second lines,
wherein the lower electrode layers are configured to carry a voltage or a current between a corresponding one of the first lines and said each of the memory cells,
wherein the selection element layers are configured to control accessing to the variable resistance layers,
wherein the middle electrode layers are configured to physically separate the selection element layers from the variable resistance layers and to electrically couple the selection element layers to the variable resistance layers,
wherein the variable resistance layers are configured to switch between different resistance states according to an applied voltage or current,
wherein each of the upper electrode layers is configured to provide a transmission path of a voltage or a current between said each of the variable resistance layers and a corresponding one of the second lines,
wherein the variable resistance layers are formed by a sputtering process using a sputtering target, the sputtering target including a carbon-doped GeSbTe alloy,
wherein, for the carbon-doped GeSbTe alloy, a condition of Y=X×(Z/100) is satisfied, and
wherein an average grain diameter of a GeSbTe alloy after sintering is X (μm), an average grain diameter of carbon after the sintering is Y (μm), and a content of carbon is Z (at %).

8. The method of claim 7 , wherein the selection element layer has a single-layered structure, or a multi-layered structure that exhibits a selection element characteristic using a combination of two or more layers.

9. The method of claim 7 , wherein the average grain diameter of the GeSbTe alloy after the sintering is in a range of 0.5 μm to 30 μm.

10. The method of claim 7 , wherein the carbon-doped GeSbTe alloy includes 5 to 25 at % of germanium, 20 to 40 at % of antimony, 40 to 60 at % of tellurium, and 0.1 to 20 at % of carbon.

Assignees

• Sk Hynix Inc

Inventors

• Ahn Jun Ku

Classifications

• H10B63/10

  Phase change RAM [PCRAM, PRAM] devices · CPC title

• H10N70/026 Primary

  by physical vapor deposition, e.g. sputtering · CPC title

• C23C14/0623 Primary

  Sulfides, selenides or tellurides · CPC title

• C23C14/3414 Primary

  Metallurgical or chemical aspects of target preparation, e.g. casting, powder metallurgy · CPC title

• H10B63/00

  Resistance change memory devices, e.g. resistive RAM [ReRAM] devices · CPC title