Three-terminal electro-chemical memory cell with vertical structure for neuromorphic computation and memory cell array including the same

Patent metadata

Field	Value
Publication number	US-11963372-B2
Application number	US-202117469372-A
Country	US
Kind code	B2
Filing date	Sep 8, 2021
Priority date	May 18, 2021
Publication date	Apr 16, 2024
Grant date	Apr 16, 2024

Abstract

Disclosed is a three-terminal electro-chemical memory cell with a vertical structure for neuromorphic computation, including a circumferential hole, first and second conductive electrode layers sequentially stacked along an outer surface of the circumferential hole, an electrolyte layer formed along an inner surface of the circumferential hole and connected to one end of each of the first and second conductive electrode layers, and a gate electrode disposed parallel to the electrolyte layer in an inner surface direction of the circumferential hole.

First claim

What is claimed is:

1. A three-terminal electro-chemical memory device with a vertical structure for neuromorphic computation, comprising:
a circumferential hole;
first and second conductive electrode layers sequentially stacked along an outer surface of the circumferential hole;
an electrolyte layer formed along an inner surface of the circumferential hole and connected to one end of each of the first and second conductive electrode layers;
a gate electrode layer disposed parallel to the electrolyte layer in an inner surface direction of the circumferential hole; and
an insulator filled in an inner surface of the gate electrode layer.

2. The three-terminal electro-chemical memory cell of claim 1 , wherein the first and second conductive electrode layers constitute a disk shape in contact with the outer surface of the circumferential hole, and are spaced apart through another insulator.

3. The three-terminal electro-chemical memory cell of claim 1 , wherein the electrolyte layer is formed as a circumferential surface inside a circumferential channel layer in contact with the inner surface of the circumferential hole.

4. The three-terminal electro-chemical memory cell of claim 3 , further comprising:
an ion reservoir layer in contact with the inner surface of the electrolyte layer and formed as the circumferential surface.

5. The three-terminal electro-chemical memory cell of claim 4 , wherein the ion reservoir layer is made of Mo oxide.

6. A three-terminal electro-chemical memory cell with a vertical structure for neuromorphic computation, comprising:
a circumferential hole;
first and second conductive electrode layers sequentially stacked along an outer surface of the circumferential hole;
a channel layer formed along an inner surface of the circumferential hole and connected to one end of each of the first and second conductive electrode layers; and
a gate electrode layer disposed parallel to the channel layer in an inner surface direction of the circumferential hole; and
an insulator filled in an inner surface of the gate electrode layer.

7. The three-terminal electro-chemical memory cell of claim 6 , wherein the first and second conductive electrode layers constitute a disk shape in contact with the outer surface of the circumferential hole, and are spaced apart through another insulator.

8. The three-terminal electro-chemical memory cell of claim 6 , wherein the channel layer is formed between the inner surface of the circumferential hole and an outer surface of an electrolyte layer formed as a circumferential surface.

9. The three-terminal electro-chemical memory cell of claim 8 , further comprising:
an ion reservoir layer in contact with the inner surface of the electrolyte layer and formed as the circumferential surface.

10. The three-terminal electro-chemical memory cell of claim 9 , wherein the ion reservoir layer is made of Mo oxide.

11. A circumferential three-terminal memory cell with a vertical structure for neuromorphic computation, comprising:
a channel layer, an electrolyte layer, and a gate electrode layer sequentially forming a circumferential surface toward an inside;
first and second conductive electrode layers sequentially stacked in a disk shape on an outside of the circumferential surface; and
an insulator filled in an inner surface of the gate electrode layer.

12. An array of three-terminal memory cell with a vertical structure for neuromorphic computation, comprising:
a channel layer, an electrolyte layer, and a gate electrode layer sequentially forming a circumferential surface toward an inside;
first and second conductive electrode layers sequentially stacked in a disk shape on an outside of the circumferential surface;
a drain line connected to the first conductive electrode layer;
a source line connected to the second conductive electrode layer;
a gate line connected to the gate electrode layer; and
an insulator filled in an inner surface of the gate electrode layer.

Assignees

• Seoul Nat Univ R&Db Foundation

Inventors

• Lee Yun Seog
• Lee Hyunjoon

Classifications

• H10B63/845 Primary

  the switching components being connected to a common vertical conductor · CPC title

• G06N3/063

  using electronic means · CPC title

• H10B63/34

  of the vertical channel field-effect transistor type · CPC title

• H10N70/24

  based on migration or redistribution of ionic species, e.g. anions, vacancies · CPC title

• H10B63/84 Primary

  arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays · CPC title