Integrated circuit read only memory (ROM) structure

Patent metadata

Field	Value
Publication number	US-11963348-B2
Application number	US-202217818954-A
Country	US
Kind code	B2
Filing date	Aug 10, 2022
Priority date	Mar 5, 2021
Publication date	Apr 16, 2024
Grant date	Apr 16, 2024

Abstract

A method of making a ROM structure includes the operations of forming an active area having a channel, a source region, and a drain region; depositing a gate electrode over the channel; depositing a conductive line over at least one of the source region and the drain region; adding dopants to the source region and the drain region of the active area; forming contacts to the gate electrode, the source region, and the drain; depositing a power rail, a bit line, and at least one word line of the integrated circuit against the contacts; and dividing the active area with a trench isolation structure to electrically isolate the gate electrode from the source region and the drain region.

First claim

We claim:

1. A method of making an integrated circuit read only memory (ROM) structure, comprising:
forming a ROM transistor by
implanting an active area in a substrate to define a channel, a source region, and a drain region;
depositing a gate electrode over the channel;
removing a portion of the gate electrode and an underlying portion of the channel to form a trench separating a first portion of the active area and a second portion of the active area;
depositing a dielectric material to fill the trench and form a trench isolation structure to isolate the first portion of the active area from the second portion of the active area;
depositing a conductive line over at least one of the source region and the drain region;
adding dopants to the source region and the drain region of the active area;
forming a plurality of contacts comprising a gate electrode contact, a source region contact, and a drain region contact; and
depositing a power rail, a bit line, and at least one word line of the integrated circuit over the contacts.

2. The method of claim 1 , wherein
forming the trench isolation structure to electrically isolate the first portion of the active area from the second portion of the active area further comprises:
depositing a layer of patterning material over the gate electrode;
developing the layer of patterning material to expose the gate electrode through an opening in the layer of patterning material;
etching an opening through the gate electrode to expose the substrate; and
filling the opening with the dielectric material.

3. The method of claim 2 , further comprising
exposing a material below the channel, wherein filling the opening with the dielectric material further comprises depositing the dielectric material on the substrate.

4. The method of claim 2 , wherein
forming the trench isolation structure further comprises dividing the gate electrode into multiple portions using an etching process.

5. The method of claim 4 , further comprising:
etching a first opening through the gate electrode; and
filling the opening with a dielectric material.

6. The method of claim 1 , further comprising
configuring the ROM transistor by forming a gate electrode tie-off contact configured to electrically connect the gate electrode to a power rail, and wherein
the gate electrode tie-off contact, the gate electrode contact, the source region contact, and the drain region contact are formed simultaneously.

7. The method of claim 1 , further comprising:
depositing an inter-layer dielectric (ILD) over the conductive line and the gate electrode;
etching a first opening through the ILD to expose a first source contact;
etching a second opening through the ILD to expose a first drain contact;
etching a third opening through the ILD to expose a gate electrode contact;
filling the first opening through the ILD to make a power rail;
filling the second opening to form a bit line; and
filling the third opening to form a word line.

8. The method of claim 7 , wherein:
etching the first opening further comprises exposing a second source contact and
filling the first opening further comprises making a power rail which electrically connects the first source contact to the second source contact.

9. The method of claim 8 , wherein
etching a first opening through the gate electrode further comprises exposing a portion of the substrate below the gate electrode and
filling the first opening with the dielectric material further comprises depositing the dielectric material on the portion of the substrate.

10. A method of manufacturing an integrated circuit structure, comprising:
forming a first transistor comprising a first gate electrode, a first channel, a first source, a first source conductive line over the first source, a first drain, and a first drain conductive line over the first drain;
forming a second transistor comprising a second gate electrode, a second channel, a second drain, the first source, and a second drain conductive line over the second drain;
removing a portion of the second gate electrode and an underlying portion of the second channel to form a trench separating the first source and the second drain;
depositing a dielectric material to fill the trench and isolate the first source and the second drain; and
forming a bit line that electrically connects the first drain conductive line to the second drain conductive line.

11. The method according to claim 10 , further comprising:
positioning the first gate electrode relative to the second gate electrode whereby the first and second gate electrodes are separated by one conductive line separation interval.

12. The method according to claim 10 , further comprising:
positioning the first gate electrode relative to the second gate electrode whereby the first and second gate electrodes are separated by two conductive line separation intervals.

13. The method according to claim 10 , further comprising:
forming a power rail; and
electrically connecting the first source conductive line and a second source conductive line to the power rail.

14. The method according to claim 10 , further comprising:
forming a third gate electrode,
forming a second source on a first side of the third gate electrode;
forming a second source conductive line electrically connected to the first source conductive line;
forming a third drain on a second side of the third gate electrode opposite the second source; and
forming a third drain conductive line.

15. The method according to claim 14 , further comprising:
forming a third transistor with the third drain, the third gate electrode, and the second drain; and
configuring the second drain of the second transistor to provide a bit value for the third transistor.

16. A method of manufacturing an integrated circuit structure, comprising:
forming a first drain contact;
forming a drain conductive line electrically connected to the first drain contact;
forming a first transistor comprising:
forming a first gate electrode,
forming a first gate electrode contact,
forming a first source,
forming a first source conductive line electrically connected to the first source,
forming a first source contact electrically connected to the first source conductive line,
forming a first drain electrically connected to the drain conductive line, and
forming a power rail electrically connected to the first source contact and a first gate electrode tie-off contact, wherein the first gate electrode tie-off contact electrically connects the power rail to the first gate electrode; and

forming a second transistor comprising:
forming a second gate electrode,
forming a second gate electrode contact connected to the second gate electrode,
forming a second source,
forming a second source conductive line connected to the second source,
forming a second source contact connected to the second source conductive line and the power rail;
forming a second drain electrically connected to the drain conductive line; and
forming a second gate electrode tie-off contact in electrical connection with both the second gate electrode and the power rail.

17. The method according to claim 16 , further comprising:
forming the first and second gate electrodes comprises forming a plurality of semiconductor nanosheets separated by a gate dielectric material.

18. The method according to claim 16 , further comprising:
positioning the first gate electrode relative to the second gate electrode to provide a gate electrode separation

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Geng-Cing
• Lu Ze-Sian
• Chang Meng-Sheng
• Huang Chia-En
• Yang Jung-Ping
• Chen Yen-Huei

Classifications

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/427

  Power or ground buses · CPC title

• H10D84/0149

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title