Tie off device

Patent metadata

Field	Value
Publication number	US-2020402979-A1
Application number	US-202016879166-A
Country	US
Kind code	A1
Filing date	May 20, 2020
Priority date	Jun 19, 2019
Publication date	Dec 24, 2020
Grant date	—

Abstract

An integrated circuit device includes a first power rail, a first active area extending in a first direction, and a plurality of gates contacting the first active area and extending in a second direction perpendicular to the first direction. A first transistor includes the first active area and a first one of the gates. The first transistor has a first threshold voltage (VT). A second transistor includes the first active area and a second one of the gates. The second transistor has a second VT different than the first VT. A tie-off transistor is positioned between the first transistor and the second transistor, and includes the first active area and a third one of the gates, wherein the third gate is connected to the first power rail.

First claim

What is claimed is:

1 . An integrated circuit device, comprising:
a first power rail; a first active area extending in a first direction; a plurality of gates contacting the first active area and extending in a second direction perpendicular to the first direction; a first transistor including the first active area and a first one of the gates, the first transistor having a first threshold voltage (VT); a second transistor including the first active area and a second one of the gates, the second transistor having a second VT different than the first VT; and a tie-off transistor positioned between the first transistor and the second transistor, the tie-off transistor including the first active area and a third one of the gates, wherein the third gate is connected to the first power rail.

2 . The integrated circuit device of claim 1 , wherein the third gate is connected to the first power rail by a first conductive via.

3 . The integrated circuit device of claim 1 , wherein the first active area includes a fin.

4 . The integrated circuit device of claim 1 , wherein the tie-off transistor is a PMOS transistor, and where the first power rail is a VDD power rail.

5 . The integrated circuit device of claim 1 , wherein the tie-off transistor is an NMOS transistor, and where the first power rail is a VSS power rail.

6 . The integrated circuit device of claim 4 , wherein the first and second transistors are PMOS transistors.

7 . The integrated circuit device of claim 5 , wherein the first and second transistors are NMOS transistors.

8 . The integrated circuit device of claim 6 , wherein the plurality of gates are poly gates, the integrated circuit further comprising:
a VSS power rail; a second active area extending in a first direction, wherein the plurality of poly gates contact the second active area; a first NMOS transistor including the second active area and the first poly gate, the first NMOS transistor having the first VT; a second NMOS transistor including the second active area and the second poly gate, the second NMOS transistor having the second VT; and an NMOS tie-off transistor positioned between the first NMOS transistor and the second NMOS transistor, the NMOS tie-off transistor including the first active area and the third poly gate, wherein the third poly gate is connected to the VSS power rail, and wherein the third poly gate includes a cut poly between the first and second active areas.

9 . The integrated circuit device of claim 8 , wherein the third poly gate is connected to the VSS power rail by a second conductive via.

10 . The integrated circuit device of claim 9 , wherein the third poly gate is connected to the VSS power rail by a metal layer and a third conductive via.

11 . A semiconductor device, comprising:
a first power rail; a second power rail; a first fin extending in a first direction; a first PMOS transistor including the first fin and a first gate, the first PMOS transistor having a first threshold voltage (VT), the first gate extending in a second direction perpendicular to the first direction; a second PMOS transistor including the first fin and a second gate extending in the second direction, the second PMOS transistor having a second VT different than the first VT, and wherein the second gate is connected to the first power rail; a second fin extending in the first direction; a first NMOS transistor including the second fin and the first gate, the first NMOS transistor having the first VT; a second NMOS transistor including the second fin and the second gate, the second NMOS transistor having the second VT, and wherein the second gate is connected to the second power rail.

12 . The integrated circuit device of claim 11 , wherein the first gate is connected to the second power rail, and wherein the second gate is connected to the first power rail through the first PMOS transistor.

13 . The integrated circuit device of claim 11 , wherein the first gate is connected to the first power rail, and wherein the second gate is connected to the second power rail through the first NMOS transistor.

14 . The integrated circuit device of claim 12 , wherein the second gate is connected to the first PMOS transistor through a metal layer extending in the first direction and a metal strip extending in the second direction.

15 . The integrated circuit device of claim 11 , further comprising:
a third PMOS transistor including the first fin and a third gate, the third PMOS transistor having the second VT, wherein the second PMOS transistor is between the first and third PMOS transistors; a third NMOS transistor including the first fin and the third gate, the third NMOS transistor having the second VT, wherein the second NMOS transistor is between the first and third NMOS transistors.

16 . The integrated circuit device of claim 11 , wherein the first, second and third gates comprise respective first, second and third poly gates, and wherein the second poly gate includes a cut poly between the first and second fins, and wherein the second poly gate is directly connected to the first power rail.

17 . A method, comprising:
forming a first active area on a substrate, the first active area including a first threshold voltage (VT) region and a second VT region; forming a first gate contacting the first VT region of the first active area to form a first transistor having a first VT; forming a second gate contacting the second VT region of the first active area to form a second transistor having a second VT different than the first VT; forming a third gate contacting the first active area between the first gate and the second gate to form a tie-off transistor positioned between the first transistor and the second transistor; and connecting the third gate to a power rail to maintain the tie-off transistor in an off state.

18 . The method of claim 17 , wherein the tie-off transistor is a PMOS transistor and wherein connecting the third gate to the power rail to maintain the tie-off transistor in the off state includes connecting the third gate to a VDD power rail.

19 . The method of claim 18 , wherein connecting the third gate to the VDD power rail includes providing a conductive via extending between the third gate and the VDD power rail.

20 . The method of claim 18 , wherein the first and second transistors and the tie-off transistor are PMOS transistors, the method further comprising:
forming a second active area on the substrate, the second active area including the first VT region and the second VT region; forming the first gate to further contact second active area to form a first NMOS transistor having the first VT; forming the second gate to further contact the second active area to form a second NMOS transistor having the second VT; forming the third gate to further contact the second active area to form an NMOS tie-off transistor positioned between the first NMOS transistor and the second NMOS transistor; and connecting the third gate to a second power rail to maintain the NMOS tie-off transistor in an off state.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chien Shao-Lun
• Chiang Ting-Wei
• Zhuang hui-zhong
• Sue Pin-Dai

Classifications

• H10W20/427

  Power or ground buses · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W10/051

  of isolation region based on field-effect · CPC title

• H10W10/50

  Isolation regions based on field-effect · CPC title

• H10D84/0158

  the components including FinFETs · CPC title