IC including capacitor having segmented bottom plate

Patent metadata

Field	Value
Publication number	US-11961879-B2
Application number	US-202318309999-A
Country	US
Kind code	B2
Filing date	May 1, 2023
Priority date	Aug 23, 2021
Publication date	Apr 16, 2024
Grant date	Apr 16, 2024

Abstract

An IC includes a substrate including circuitry configured to provide a receiver or a transmitter circuit. A metal stack is over the semiconductor surface including a top metal layer and a plurality of lower metal layers. An isolation capacitor includes the top metal layer as a top plate that is electrically connected to a first node; and a top dielectric layer on the top plate with a top plate dielectric aperture. One of the plurality of lower metal layers provides a bottom plate that includes a plurality of spaced apart segments. A capacitor dielectric layer is between the top and bottom plate. The segments include a first segment electrically connected to a second node and at least a second segment electrically connected to a third node, with separation regions located between adjacent spaced apart segments. The top plate covers at least a portion of each of the separation regions.

First claim

What is claimed is:

1. A method of forming an integrated circuit (IC), comprising:
forming stacked metal layers on a semiconductor substrate including circuitry with nodes, the stacked metal layers including a first metal layer and a second metal layers located under the first metal layer; and
forming a segmented isolation capacitor, including:
forming a bottom plate of the segmented isolation capacitor based on the second metal layer, the bottom plate including a plurality of spaced apart segments, wherein a first segment of the plurality of spaced apart segments is electrically connected to a first node of the nodes, and wherein a second segment of the plurality of spaced apart segments is electrically connected to a second node of the nodes;
forming a capacitor dielectric layer of the segmented isolation capacitor over the bottom plate; and
forming a top plate of the segmented isolation capacitor based on the first metal layer, the top plate covering at least a portion of the plurality of spaced apart segments, wherein the top plate is electrically connected to a third node of the nodes.

2. The method of claim 1 , wherein the IC further comprises another isolation capacitor.

3. The method of claim 1 , further comprising:
forming an isolation ring based on the second metal layer, the isolation ring surrounding the plurality of spaced apart segments, wherein the isolation ring is electrically connected to a ground of the IC.

4. The method of claim 1 , further comprising:
forming a top dielectric layer over the top plate, wherein the top dielectric layer includes an aperture exposing a portion of the top plate.

5. The method of claim 4 , wherein the top dielectric layer comprises a first dielectric layer on a second dielectric layer.

6. The method of claim 1 , wherein the first metal layer corresponds to a topmost metal layer of the stacked metal layers.

7. The method of claim 1 , wherein the circuitry includes a receiver circuit or a transmitter circuit.

8. A method, comprising:
forming a bottom plate of a segmented capacitor using a first metal layer over a semiconductor substrate including circuitry with nodes, wherein:
the bottom plate includes a plurality of spaced apart segments;
a first segment of the plurality of spaced apart segments is electrically connected to a first node of the nodes; and
a second segment of the plurality of spaced apart segments is electrically connected to a second node of the nodes;

forming a dielectric layer of the segmented capacitor over the bottom plate; and
forming a top plate of the segmented capacitor over the dielectric layer using a second metal layer, wherein:
the top plate is electrically connected to a third node of the nodes; and
the top plate covers at least a portion of the plurality of spaced apart segments.

9. The method of claim 8 , wherein forming the bottom plate includes forming an isolation ring using the first metal layer, wherein:
the isolation ring surrounds the plurality of spaced apart segments; and
the isolation ring is electrically connected to a ground of the circuitry.

10. The method of claim 8 , wherein the second metal layer is a topmost metal layer of a plurality of metal layers over the semiconductor substrate.

11. The method of claim 8 , wherein the dielectric layer includes a first dielectric layer on a second dielectric layer.

12. The method of claim 8 , wherein the dielectric layer is a first dielectric layer, the method further comprising:
forming a second dielectric layer over the top plate, wherein the second dielectric layer includes an aperture exposing a portion of the top plate.

13. The method of claim 8 , wherein the segmented capacitor is a first capacitor, the method further comprising forming a second capacitor over the semiconductor substrate.

14. The method of claim 8 , wherein the circuitry includes a receiver circuit or a transmitter circuit.

15. The method of claim 8 , wherein at least two adjacent segments of the plurality of spaced apart segments are separated by a gap ranging between 0.5 μm to 5 μm.

16. The method of claim 8 , wherein the segmented capacitor has a total capacitance of 10 to 1,000 fF.

17. The method of claim 8 , wherein a thickness of the dielectric layer is at least 4 μm.

18. The method of claim 8 , wherein the dielectric layer includes silicon dioxide.

19. The method of claim 8 , further comprising:
connecting a bond wire between the top plate and a pin external to the semiconductor substrate.

20. The method of claim 19 , further comprising:
encapsulating the semiconductor substrate, the segmented capacitor, and the bond wire using a mold compound.

Assignees

• Texas Instruments Inc

Inventors

• West Jeffrey
• Das Mrinal
• Williams Byron
• Bonifield Thomas
• Franke Maxim

Classifications

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/59

  Bond pads specially adapted therefor · CPC title